Patent number: 6636882
Abstract: A multiplier for obtaining the product of elements in a Galois Field. The multiplier performs the multiplication of two n-bit elements, A(an-1, an-2, . . . , a3, a2, a1, a0) and B(bn-1, bn-2, . . . , b3, b2, b1, b0) in the Galois Field to yield the product C(cn-1, cn-2, . . . , c3, c2, c1, c0), wherein n≧1 ai(i=0˜n-1), bj(j=0˜n-1), and ck(k=O˜n-1) are all binary bits. The multiplier includes: an AND planer, for performing an AND logic operation of every bit ai in A(an-1, an-2, . . . , a3, a2, a1, a0) and every bit bj in B(bn-1, bn-2, . . . , b3, b2, b1, b0) to obtain (an-1bn-1, an-1bn-2, . . . , an-1b0, an-2bn-1, an-2bn-2, . . . , an-2b0, a0bn-1, a0bn-2, . . . , a0b0); and an XOR planer, for performing an XOR logic operation of the output from the AND planer to obtain C(cn-1, cn-2, . . . , c3, c2, c1, c0).
Type:
Grant
Filed:
January 14, 2000
Date of Patent:
October 21, 2003
Assignee:
Via Technologies, Inc.
Inventors:
Wei-Ming Su, Shin Yung Chen Banyan, Yi-Lin Lai