Patents by Inventor Yi Ling

Yi Ling has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250149071
    Abstract: A sensing amplifier circuit includes first and second P-type transistors and first and second N-type transistors. The first P-type transistor includes a gate coupled to an input node, a source and a bulk coupled to a first node, and a drain coupled to an output node. The second P-type transistor includes a gate coupled to an inverted reading-triggered signal, a source coupled to a voltage source, and a drain coupled to the first node. The first N-type transistor includes a gate coupled to the input node, a drain coupled to the output node, and a source coupled to ground. The second N-type transistor includes a gate receiving the inverted reading-triggered signal, a drain coupled to the output node, and a source coupled to the ground. The first P-type transistor includes an N-type well region that is electrically connected to the source and bulk of the first P-type transistor.
    Type: Application
    Filed: November 2, 2023
    Publication date: May 8, 2025
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Po-Yuan TANG, Chih-Chuan KE, Jian-Yuan HSIAO, Yi-Ling HUNG
  • Publication number: 20250142719
    Abstract: A flexible circuit board designed for chip integration is provided. The flexible circuit board includes an insulating substrate, a conductive copper layer, a first tin layer, a second tin layer, and a first solder resist layer. The first tin layer has a first tin thickness, and the second tin layer has a greater second tin thickness. A first tin surface of the first tin layer and a second tin surface of the second tin layer are substantially level.
    Type: Application
    Filed: October 8, 2024
    Publication date: May 1, 2025
    Inventors: Chiu-Hong Lai, Wen Ping Hsu, Yi Ling Hsieh, Dong-Sheng Li, Yi Ren Chian, San Lee, Pei-Ying Lee, Ting-Yi Kuo
  • Publication number: 20250132246
    Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, a method includes receiving a workpiece comprising a first transistor and a second transistor formed over a first side of a substrate, forming a first multi-layer interconnect (MLI) structure over the first side of the substrate, wherein the first MLI structure comprising a first plurality of metal lines and a first plurality of vias, after the forming of the first MLI structure, forming a source/drain contact directly under a source/drain feature of the first transistor, and forming a second MLI structure under the source/drain contact and under a second side of the substrate, the second side being opposite the first side, wherein the MLI structure comprises a second plurality of metal lines and a second via, a thickness of the second via is greater than a thickness of one of the first plurality of vias.
    Type: Application
    Filed: October 20, 2023
    Publication date: April 24, 2025
    Inventors: Yi Ling Liu, Tsung-Chieh Hsiao, Liang-Wei Wang, Dian-Hau Chen
  • Publication number: 20250125520
    Abstract: A wearable device includes a first radiation metal element, a second radiation metal element, a ground metal element, a third radiation metal element, and a carrier element. The first radiation metal element is coupled to a positive feeding point. The second radiation metal element is coupled to the positive feeding point. The ground metal element is coupled to a negative feeding point. The third radiation metal element is adjacent to the ground metal element. A coupling gap is formed between the third radiation metal element and the ground metal element. The first radiation metal element, the second radiation metal element, the ground metal element, and the third radiation metal element are disposed on the carrier element. An antenna structure is formed by the first radiation metal element, the second radiation metal element, the ground metal element, and the third radiation metal element.
    Type: Application
    Filed: December 28, 2023
    Publication date: April 17, 2025
    Inventors: Yi-Ling TSENG, Chin-Lung TSAI, Chung-Ting HUNG, Kai-Hsiang CHANG, Yu-Chen ZHAO
  • Publication number: 20250126848
    Abstract: A flash memory device and method of making the same are disclosed. The flash memory device is located on a substrate and includes a floating gate electrode, a tunnel dielectric layer located between the substrate and the floating gate electrode, a smaller length control gate electrode and a control gate dielectric layer located between the floating gate electrode and the smaller length control gate electrode. The length of a major axis of the smaller length control gate electrode is less than a length of a major axis of the floating gate electrode.
    Type: Application
    Filed: December 20, 2024
    Publication date: April 17, 2025
    Inventors: Yu-Chu LIN, Chi-Chung JEN, Wen-Chih CHIANG, Yi-Ling LIU, Huai-jen TUNG, Keng-Ying LIAO
  • Publication number: 20250125530
    Abstract: An antenna structure includes a feeding radiation element, a first radiation element, a second radiation element, a third radiation element, and a carrier element. The feeding radiation element has a feeding point. The first radiation element is coupled to the feeding radiation element. The first radiation element has a meandering structure. The second radiation element is coupled to the feeding radiation element. The second radiation element is adjacent to the first radiation element. The third radiation element is coupled to the ground voltage. The third radiation element is adjacent to the second radiation element. The feeding radiation element, the first radiation element, the second radiation element, and the third radiation element are disposed on the carrier element.
    Type: Application
    Filed: December 28, 2023
    Publication date: April 17, 2025
    Inventors: Chun-I CHENG, Chung-Ting HUNG, Chin-Lung TSAI, Yi-Ling TSENG, Yu-Chen ZHAO, Kai-Hsiang CHANG
  • Publication number: 20250088286
    Abstract: Embodiments of a method and apparatus for communications are disclosed. In an embodiment, a communications device includes a controller configured to perform periodic or aperiodic in-device interference mitigation and a wireless transceiver configured to conduct wireless communications in response to the periodic or aperiodic in-device interference mitigation.
    Type: Application
    Filed: August 30, 2024
    Publication date: March 13, 2025
    Inventors: Liwen Chu, Kiseon Ryu, Huizhao Wang, Hongyuan Zhang, Yi-Ling Chao
  • Publication number: 20250082818
    Abstract: An artificial dressing, use of artificial dressing for promoting wound healing and method of manufacturing artificial dressing are disclosed. The artificial dressing comprises a gelatin, a polysorbate 20 and a glutaraldehyde for promoting wound healing. The manufacturing method of the artificial dressing comprises the steps of enabling the composition of the gelatin, the polysorbate 20 and the glutaraldehyde to perform a foaming step, a molding step and a freeing step in sequence. The artificial dressing has obvious pores and is capable of absorbing a liquid weight about 25-35 times of its body weight. After thermal disintegration experiments and adhesion tests, disintegration of the artificial dressing is not observed, and in animal experiments, compared with commercially available dressings, the artificial dressing of the invention is capable of accelerating wound healing when applied dryly; and capable of proliferating functional tissues of the wound when applied wetly.
    Type: Application
    Filed: September 5, 2024
    Publication date: March 13, 2025
    Applicant: Anti-Microbial Savior BioteQ Co., Ltd.
    Inventors: Yi-Ju Tsai, YING-TING YEH, YI-LING HONG, MENG-YI BAI
  • Patent number: 12247924
    Abstract: Disclosed herein is a composite material suitable for use in surface-enhanced Raman scattering, the material comprising a substrate layer having a surface; a plurality of layers of core-shell particles formed on the surface of the substrate layer, wherein the core is formed from a plasmonic metal nanoparticle, and the shell is formed from a metal-organic framework (MOF), and wherein the plurality of layers of core-shell particles provide a thickness of from 0.5 to 10 um on the surface of the substrate layer. In specific embodiments, the plasmonic metal nanoparticles are silver nanocubes, and the MOF is ZIF-8.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: March 11, 2025
    Assignee: Nanyang Technological University
    Inventors: Xing Yi Ling, Gia Chuong Phan Quang
  • Publication number: 20250071860
    Abstract: A method for operation of a first communication device in a wireless local area network (WLAN) communication channel, having a plurality of component channels, between the first communication device and a second communication device is described. A first physical layer (PHY) protocol data unit (PPDU) and a second PPDU, distinct from the first PPDU, are generated. The first PPDU and second PPDU are transmitted simultaneously to the second communication device over the WLAN communication channel, including: transmitting the first PPDU via a first component channel within a first radio frequency (RF) channel segment that occupies a first frequency bandwidth, and transmitting the second PPDU via a second component channel within a second RF channel segment that occupies a second frequency bandwidth that does not overlap the first frequency bandwidth segment, and is separated from the first frequency bandwidth segment by a frequency gap.
    Type: Application
    Filed: November 11, 2024
    Publication date: February 27, 2025
    Inventors: Liwen CHU, Hongyuan ZHANG, Hui-Ling LOU, Yi-Ling CHAO
  • Publication number: 20250062185
    Abstract: An electronic package and a manufacturing method thereof are provided, in which an offset suppression layer is formed on a carrier, a first electronic element and a second electronic element are respectively disposed on the offset suppression layer, and an encapsulant is formed on the offset suppression layer to respectively cover the first electronic element and the second electronic element. The offset suppression layer effectively suppresses or prevents possible offset caused by the encapsulant to the first electronic element and the second electronic element, thereby avoiding yield loss of the semiconductor package.
    Type: Application
    Filed: December 13, 2023
    Publication date: February 20, 2025
    Inventors: Yi-Ling CHEN, Kuan-Wei CHUANG
  • Publication number: 20250041264
    Abstract: The object of the present disclosure is to provide a method for treating diabetes by using an Antrodia camphorata compound, wherein the Antrodia camphorata compound is shown in the following formula 1: or the pharmacologically acceptable salts of the formula 1.
    Type: Application
    Filed: January 24, 2024
    Publication date: February 6, 2025
    Inventors: Mao-tien Kuo, Yin-yu Kuo, Hui-ling Tseng, Tai-lin Tseng, Wan-ping Tseng, Yi-ling Ye, Li-shian Shi, Ya-hong Lin
  • Publication number: 20250046756
    Abstract: Interconnect structures for front-to-front stacked chips/dies and methods of fabrication thereof are disclosed herein. An exemplary system on integrated circuit (SoIC) includes a first die that is front-to-front bonded with a second die, for example, by bonding a first topmost metallization layer of a first frontside multilayer interconnect of the first die to a second topmost metallization layer of a second frontside multilayer interconnect of the second die. A through via extends partially through the first frontside multilayer interconnect of the first die, through a device layer of the first die, through a backside power rail of the first die, and through a carrier substrate. The backside power rail is between the carrier substrate and the device layer, and the backside power rail may be a portion of a backside multilayer interconnect of the first die. The through via may be connected to a redistribution layer (RDL) structure.
    Type: Application
    Filed: January 4, 2024
    Publication date: February 6, 2025
    Inventors: Tsung-Chieh Hsiao, Yi Ling Liu, Ke-Gang Wen, Yu-Bey Wu, Liang-Wei Wang
  • Patent number: 12218253
    Abstract: A flash memory device and method of making the same are disclosed. The flash memory device is located on a substrate and includes a floating gate electrode, a tunnel dielectric layer located between the substrate and the floating gate electrode, a smaller length control gate electrode and a control gate dielectric layer located between the floating gate electrode and the smaller length control gate electrode. The length of a major axis of the smaller length control gate electrode is less than a length of a major axis of the floating gate electrode.
    Type: Grant
    Filed: April 15, 2023
    Date of Patent: February 4, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yu-Chu Lin, Chi-Chung Jen, Wen-Chih Chiang, Yi-Ling Liu, Huai-Jen Tung, Keng-Ying Liao
  • Publication number: 20250038074
    Abstract: A method includes forming a first multilayer interconnect structure over a first side of a device layer, forming a first portion of a second multilayer interconnect structure under a second side of the device layer, forming a trench that extends through the second dielectric layer, the device layer, and the first dielectric layer, forming a conductive structure in the trench, and forming a second portion of the second multilayer interconnect structure under the first portion of the second multilayer interconnect structure. The second portion of the second multilayer interconnect structure includes patterned metal layers disposed in a third dielectric layer, and wherein one or more of the patterned metal layers are in electrical connection with the conductive structure.
    Type: Application
    Filed: December 1, 2023
    Publication date: January 30, 2025
    Inventors: Tsung-Chieh Hsiao, Yi Ling Liu, Yun-Sheng Li, Ke-Gang Wen, Yu-Bey Wu, Liang-Wei Wang, Dian-Hau Chen
  • Publication number: 20250038129
    Abstract: An inner lead structure of a flexible circuit board includes a flexible substrate, a circuit layer and a dummy circuit layer. A chip mounting area defined on the flexible substrate is provided for a chip, contacting locations defined within the chip mounting area are provided for conductive elements of the chip. The circuit layer includes inner leads, ends of the inner leads are arranged on the contacting locations and provided to be electrically connected to the conductive elements. At least one of first dummy lines of the dummy circuit layer is arranged in a space between the adjacent inner leads. The space having a distance greater than 50 um is divided into multiple spaces having distances not greater than 50 um. Proportion of the spaces without the first dummy lines and having a distance greater than 50 um is less than 0.5% in all spaces.
    Type: Application
    Filed: March 27, 2024
    Publication date: January 30, 2025
    Inventors: Wen-Ping Hsu, Yi-Ling Hsieh
  • Patent number: 12189281
    Abstract: A projection device includes a plurality of solid-state lighting sources driven by a DC drive power to sequentially provide a first light generated by a first number of light sources, a second light generated by a second number of light sources and a third light generated by a third number of light sources within a response cycle; and a color wheel having a first block, a second block and a third block, respectively corresponding to the first to third lights, so that the projection device sequentially outputs a first color light with a first brightness, a second color light with a second brightness and a third color light with a third brightness. The brightness of the first to third lights is controlled by number of light sources to be turn on.
    Type: Grant
    Filed: September 19, 2023
    Date of Patent: January 7, 2025
    Assignee: Qisda Corporation
    Inventors: Jia-Ming Zhang, Yi-Ling Lo, Ching-Tze Huang
  • Patent number: 12183994
    Abstract: An antenna structure includes a main ground plane, a protruding ground plane, a feeding radiation element, a connection radiation element, a shorting radiation element, a first radiation element, and a second radiation element. The protruding ground plane is coupled to the main ground plane. The feeding radiation element has a feeding point. The connection radiation element is coupled to the feeding radiation element. The connection radiation element is further coupled through the shorting radiation element to the protruding ground plane. The first radiation element is coupled to the feeding radiation element. The second radiation element is coupled to the connection radiation element. The protruding ground plane further includes an extension portion. The first radiation element is adjacent to the extension portion of the protruding ground plane.
    Type: Grant
    Filed: January 12, 2023
    Date of Patent: December 31, 2024
    Assignee: QUANTA COMPUTER INC.
    Inventors: Ying-Cong Deng, Chung-Ting Hung, Chin-Lung Tsai, Yi-Ling Tseng, Yu-Chen Zhao, Yi-Chih Lo
  • Patent number: 12173135
    Abstract: A plasticizer, which is biodegradable, has a molecule including a central structure, at least two connecting structures and at least one side-chain structure. The central structure includes at least one of a benzene derivative and at least one amino acid. The connecting structures are respectively connected to the central structure, wherein the connecting structures include a first connecting structure and a second connecting structure. The first connecting structure is an amine group, and the second connecting structure is a carboxyl group. The side-chain structure is a chain of multiple carbon atoms, and the side-chain structure is connected to at least one of the first connecting structure and the second connecting structure. An amide bond is formed as the side-chain structure connected to the amine group, and an ester bond is formed as the side-chain structure connected to the carboxyl group.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: December 24, 2024
    Assignee: LARGAN MEDICAL CO., LTD.
    Inventors: Wei-Yuan Chen, Tzu-Rong Lu, Yi-Ling Chen, Chun-Hung Teng
  • Publication number: 20240419060
    Abstract: An optical machine module includes an optical machine housing and at least one reflector adjustment mechanism. The reflector adjustment mechanism includes an adjustment base movably disposed in the optical machine housing, at least one reflector disposed on the adjustment base, a fulcrum adjustment member including a fulcrum adjustment part located outside the optical machine housing and a fulcrum connection part extending into the optical machine housing and adjustably connected to a center of the adjustment base, a first axial adjustment member including a first axial adjustment part and a first connection part, and a second axial adjustment member including a second axial adjustment part and a second connection part. The first and second axial adjustment parts are located outside the optical machine housing. The first and second connection parts extend into the optical machine housing and are adjustably connected to the adjustment base.
    Type: Application
    Filed: June 10, 2024
    Publication date: December 19, 2024
    Applicant: Qisda Corporation
    Inventors: Ko-Szu Yu, Wei-Chun Peng, Chieh-Ming Hsieh, Yi-Ling Lo