Patents by Inventor Yi-Lun Lu

Yi-Lun Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240014352
    Abstract: A light-emitting device includes a substrate including a top surface, a first side surface and a second side surface, wherein the first side surface and the second side surface of the substrate are respectively connected to two opposite sides of the top surface of the substrate; a semiconductor stack formed on the top surface of the substrate, the semiconductor stack including a first semiconductor layer, a second semiconductor layer, and an active layer formed between the first semiconductor layer and the second semiconductor layer; a first electrode pad formed adjacent to a first edge of the light-emitting device; and a second electrode pad formed adjacent to a second edge of the light-emitting device, wherein in a top view of the light-emitting device, the first edge and the second edge are formed on different sides or opposite sides of the light-emitting device, the first semiconductor layer adjacent to the first edge includes a first sidewall directly connected to the first side surface of the substrate,
    Type: Application
    Filed: September 20, 2023
    Publication date: January 11, 2024
    Inventors: Chao-Hsing CHEN, Cheng-Lin LU, Chih-Hao CHEN, Chi-Shiang HSU, I-Lun MA, Meng-Hsiang HONG, Hsin-Ying WANG, Kuo-Ching HUNG, Yi-Hung LIN
  • Publication number: 20230420041
    Abstract: The sense amplifier circuit includes a differential amplifier, a first switch, and a second switch. The differential amplifier includes a first input node, a second input node, a first output node, and a second output node. The differential amplifier amplifies a voltage difference of the first output node and the second output node according to a first input voltage of the first input node and a second input voltage of the second input node. A control node of the first (second) switch is coupled to a control line, the first (second) switch is coupled to the first (second) input node, and the first (second) switch is coupled to the first (second) output node. The first (second) switch pre-charges the first (second) input node by a first (second) output voltage of the first (second) output node while the control line is received a select signal.
    Type: Application
    Filed: June 22, 2022
    Publication date: December 28, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jui-Jen Wu, Jen-Chieh Liu, Yi-Lun Lu, Win-San Khwa, Meng-Fan Chang
  • Publication number: 20230410926
    Abstract: The disclosure introduces a shift register is configured to enter a low power mode by disabling a portion of flip-flops (FFs) that handles upper bits of input data. The shift register includes first FF(s), second FF(s) and gating circuit. The first flip-flop (FF), includes input terminal coupled to first portion of input data. The second FF includes input terminal coupled to second portion of input data, an output terminal, a clock terminal coupled to a clock signal, a power terminal coupled to a supply power. The second portion of the input data is subsequent to the first portion of the input data. The gating circuit is coupled to the output terminal of the first FF, and configured to disable the second FF for storing the second portion of a subsequent input data according to output data currently being stored in the first FF.
    Type: Application
    Filed: June 17, 2022
    Publication date: December 21, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Win-San Khwa, Yi-Lun Lu, Jui-Jen Wu, Meng-Fan Chang
  • Patent number: 11799060
    Abstract: A light-emitting device includes a substrate including a top surface, a first side surface and a second side surface, wherein the first side surface and the second side surface of the substrate are respectively connected to two opposite sides of the top surface of the substrate; a semiconductor stack formed on the top surface of the substrate, the semiconductor stack including a first semiconductor layer, a second semiconductor layer, and an active layer formed between the first semiconductor layer and the second semiconductor layer; a first electrode pad formed adjacent to a first edge of the light-emitting device; and a second electrode pad formed adjacent to a second edge of the light-emitting device, wherein in a top view of the light-emitting device, the first edge and the second edge are formed on different sides or opposite sides of the light-emitting device, the first semiconductor layer adjacent to the first edge includes a first sidewall directly connected to the first side surface of the substrate,
    Type: Grant
    Filed: February 23, 2023
    Date of Patent: October 24, 2023
    Assignee: EPISTAR CORPORATION
    Inventors: Chao-Hsing Chen, Cheng-Lin Lu, Chih-Hao Chen, Chi-Shiang Hsu, I-Lun Ma, Meng-Hsiang Hong, Hsin-Ying Wang, Kuo-Ching Hung, Yi-Hung Lin
  • Publication number: 20230317132
    Abstract: A device includes a write bit line and a read bit line extending in a first direction, and a write word line and a read word line extending in a second direction perpendicular to the first direction. The device further includes a memory cell including a write transistor and a read transistor. The write transistor includes a first gate connected to the write word line, a first source/drain connected to the write bit line, and a second source/drain connected to a data storage node. The read transistor includes a second gate connected to the data storage node, a third source/drain connected to the read bit line, and a fourth source/drain connected to the read word line.
    Type: Application
    Filed: May 23, 2022
    Publication date: October 5, 2023
    Inventors: Jen-Chieh Liu, Jui-Jen Wu, Win-San Khwa, Yi-Lun Lu, Meng-Fan Chang
  • Publication number: 20230290402
    Abstract: A memory device that includes a memory array and a pre-charge selecting circuit is introduced. The memory array includes a plurality of memory cells that are coupled to a plurality of bit lines and a plurality of word lines, wherein the plurality of word lines are configured to receive an input vector. The pre-charge selecting circuit is configured to selectively pre-charge a selected bit line according to a value of the input vector. The pre-charge selecting circuit is configured to determine whether the value of the input vector is less than a predefined threshold, and generate a gated pre-charge signal to skip pre-charging the selected bit line in response to determining that the value of the input vector is less than the predefined threshold.
    Type: Application
    Filed: June 16, 2022
    Publication date: September 14, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Win-San Khwa, Yen-Cheng Chiu, Je-Min Hung, Yi-Lun Lu, Jui-Jen Wu, Meng-Fan Chang
  • Publication number: 20230280976
    Abstract: Embodiments include monitoring a partial sum of a multiply accumulate calculation for certain conditions. When the certain conditions are met, a reduced read energy is used to read out memory contents instead of the regular read energy used. The reduced read energy may be obtained by reducing a pre-charge voltage, withholding a pre-charge voltage or providing a ground signal, and/or by reducing voltage hold times (i.e., reducing the time a pre-charge voltage is provided and/or discharged).
    Type: Application
    Filed: July 8, 2022
    Publication date: September 7, 2023
    Inventors: Win-San Khwa, Ping-Chun Wu, Yi-Lun Lu, Jui-Jen Wu, Meng-Fan Chang
  • Publication number: 20230246030
    Abstract: A semiconductor structure and forming method thereof are provided. A substrate includes a first region, a second region, and a boundary region defined between the first region and the second region. An isolation structure is disposed in the boundary region. An upper surface of the isolation structure has a stepped profile. A first boundary dielectric layer and a second boundary dielectric layer are disposed over the isolation structure. The first boundary dielectric layer is substantially conformal with respect to the stepped profile of the isolation structure.
    Type: Application
    Filed: January 28, 2022
    Publication date: August 3, 2023
    Inventors: HUNG-SHU HUANG, JHIH-BIN CHEN, MING CHYI LIU, YU-CHANG JONG, CHIEN-CHIH CHOU, JHU-MIN SONG, YI-KAI CIOU, TSUNG-CHIEH TSAI, YU-LUN LU
  • Publication number: 20230197904
    Abstract: A light-emitting device includes a substrate including a top surface, a first side surface and a second side surface, wherein the first side surface and the second side surface of the substrate are respectively connected to two opposite sides of the top surface of the substrate; a semiconductor stack formed on the top surface of the substrate, the semiconductor stack including a first semiconductor layer, a second semiconductor layer, and an active layer formed between the first semiconductor layer and the second semiconductor layer; a first electrode pad formed adjacent to a first edge of the light-emitting device; and a second electrode pad formed adjacent to a second edge of the light-emitting device, wherein in a top view of the light-emitting device, the first edge and the second edge are formed on different sides or opposite sides of the light-emitting device, the first semiconductor layer adjacent to the first edge includes a first sidewall directly connected to the first side surface of the substrate,
    Type: Application
    Filed: February 23, 2023
    Publication date: June 22, 2023
    Inventors: Chao-Hsing CHEN, Cheng-Lin LU, Chih-Hao CHEN, Chi-Shiang HSU, I-Lun MA, Meng-Hsiang HONG, Hsin-Ying WANG, Kuo-Ching HUNG, Yi-Hung LIN
  • Publication number: 20220415369
    Abstract: A sense amplifier of a memory device that includes sense amplifier circuits and a reference sharing circuit is introduced. The sense amplifier circuits are configured to sense the plurality of bit lines according to an enable signal. The reference sharing circuit includes first switches and second switches that are coupled to the reference nodes and second reference nodes of the sense amplifier circuits, respectively. The first switches and second switches are controlled according to a control signal to control a first electrical connection among the first reference nodes, and to control a second electrical connection among the second reference nodes. An operation method of the sense amplifier and a memory device including the sense amplifier are also introduced.
    Type: Application
    Filed: April 14, 2022
    Publication date: December 29, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Win-San Khwa, Yen-Cheng Chiu, Yi-Lun Lu, Jui-Jen Wu, Meng-Fan Chang
  • Patent number: 8390365
    Abstract: A charge pump system for low-supply voltage includes: a clock generator to generate a plurality of clock signals; a clock pump circuit coupled to said clock generator to generate high voltage; a level shifter coupled to said clock generator and said clock pump circuit to generate a plurality of HV (high voltage) clock signals; a main pump circuit coupled to said clock generator and said level shifter to generate output voltage.
    Type: Grant
    Filed: October 18, 2010
    Date of Patent: March 5, 2013
    Assignee: National Tsing Hua University
    Inventors: Meng-Fan Chang, Shin-Jang Shen, Yi-Lun Lu
  • Publication number: 20120092063
    Abstract: The present invention discloses a charge pump system for low-supply voltage including: a clock generator to generate a plurality of clock signals; a clock pump circuit coupled to said clock generator to generate high voltage; a level shifter coupled to said clock generator and said clock pump circuit to generate a plurality of HV (high voltage)-clock signals; a main pump circuit coupled to said clock generator and said level shifter to generate output voltage.
    Type: Application
    Filed: October 18, 2010
    Publication date: April 19, 2012
    Applicant: National Tsing Hua University
    Inventors: Meng-Fan Chang, Shin-Jang Shen, Yi-Lun Lu