Abstract: The present disclosure provides a semiconductor structure, including: a transistor, including a gate structure and a source/drain structure; a source/drain contact, disposed over the source/drain structure; a gate contact, disposed over the gate structure; and a conductive bridge, disposed over the transistor, wherein the conductive bridge overlaps the source/drain contact from a top view perspective and electrically connecting the gate contact. The present disclosure also provides a method for forming the same.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductive substrate, and a first contact plug formed on the semiconductive substrate. The semiconductor structure further includes a dielectric layer encircling the first contact plug. The semiconductor structure further includes a multilayer structure deposited on the dielectric layer and encircling the first contact plug. The dielectric layer produces a tensile stress pulling the first contact plug outward along a width direction. The multilayer structure produces a compressive stress that compensates for the tensile stress caused by the dielectric layer. A method of forming the semiconductor structure is also provided.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductive substrate, and a first contact plug formed on the semiconductive substrate. The semiconductor structure further includes a dielectric layer encircling the first contact plug. The semiconductor structure further includes a multilayer structure deposited on the dielectric layer and encircling the first contact plug. The dielectric layer produces a tensile stress pulling the first contact plug outward along a width direction. The multilayer structure produces a compressive stress that compensates for the tensile stress caused by the dielectric layer. A method of forming the semiconductor structure is also provided.

Abstract: The present disclosure provides a semiconductor structure, including: a transistor, including a gate structure and a source/drain structure; a source/drain contact, disposed over the source/drain structure; a gate contact, disposed over the gate structure; and a conductive bridge, disposed over the transistor, wherein the conductive bridge overlaps the source/drain contact from a top view perspective and electrically connecting the gate contact. The present disclosure also provides a method for forming the same.

Abstract: The present disclosure provides a semiconductor structure, including: a substrate having a gate structure; a first interlayer over the substrate; a contact adjacent to the gate structure and penetrating through the first interlayer; a dielectric layer over the first interlayer and the contact; a conductive plug electrically connecting with the gate structure and penetrating the first interlayer; and a conductive bridge electrically connecting with the conductive plug and being directly over the contact, the conductive bridge being separated from the contact by a portion of the dielectric layer.

Abstract: An apparatus comprises a circuit for measuring a gate leakage current of a plurality of transistors. A circuit is provided to apply heat to gates of the plurality of transistors. A circuit is provided to apply a single stress bias voltage to the plurality of transistors for a stress period t. The stress bias voltage is sufficient to cause a 10% degradation in a drive current of the transistor within the stress period t. A processor is provided for estimating a negative bias temperature instability (NBTI) lifetime ? of the transistor based on a relationship between the gate leakage current and one or more of the group consisting of gate voltage, gate length, gate temperature, and gate width of the plurality of transistors. The relationship is determined from data observed while applying the single stress bias voltage.

Abstract: A method includes measuring a gate leakage current of a plurality of transistors. A single stress bias voltage is applied to the plurality of transistors. The stress bias voltage causes a 10% degradation in a drive current of each transistor within a respective stress period t. One or more relationships are determined, between the measured gate leakage current and one or more of the group consisting of gate voltage, gate length, gate temperature, and gate width of the plurality of transistors, respectively. A negative bias temperature instability (NBTI) lifetime ? of the plurality of transistors is estimated, based on the measured gate leakage current and the one or more relationships.

Abstract: A new method is provided for the creation of metal plugs. After the gate electrode structures have been created on the surface of a semiconductor substrate, the Inter Level Dielectric (ILD) is deposited over the poly gates. The layer of ILD is polished, a second layer of dielectric is deposited over the layer of ILD. A stop layer is deposited over the second layer of dielectric, a Rapid Thermal Annealing (RTA) is performed to the stop layer and the thin layer of dielectric. The metal plugs are then patterned and deposited after which the process proceeds for the further creation of the interconnect metal.

Abstract: The present invention provides a method of inter-poly oxide (IPO) layer underlying a polysilicon resistor in a memory product. The IPO layer 15 is formed by a modified low pressure SACVD-O.sub.3 -TEOS process that gives the IPO layer a smoother surface and good planarization. This IPO layer gives the overlying polysilicon resistors a more uniform resistance. The method begins by providing a semiconductor structure 10. Next, in an important step, an inter-poly oxide (IPO) layer 11 is formed using low pressure ozone assisted sub-atmospheric chemical vapor deposition (SACVD O.sub.3 -TEOS) process at a pressure between about 20 and 150 torr. A polysilicon resistor 15 is then formed on said inter-poly oxide (IPO) layer. The memory device is completed by forming passivation and conductive layers thereover.

Abstract: A method for fabricating polycide contacts to semiconductor substrates, and more specifically for self-aligned contacts on substrates having field effect transistors (FETs) is achieved. After forming conventional FETs from a patterned first polysilicon layer provided with contact areas, an insulating layer is deposited. Self-aligned contact openings are etched in the insulating layer to the contact areas on the substrate, and a patterned polycide (second polysilicon/silicide) layer is used to form the electrical contacts and interconnections. However, in prior art when a photoresist mask and plasma etching are used to pattern a polycide layer, misalignment of the mask can result in notching in the sidewalls of the patterned second polysilicon layer resulting in contact damage and high leakage currents. The method of the present invention utilizes a critical pre-etch rapid thermal anneal (RTA) that essentially eliminates the notching during etching of these marginally misaligned contacts.

Abstract: A method for fabricating polysilicon load resistors, with increased resistance values, for use in SRAM cells, has been developed. An underlying, raised grid topography is used to allow the overlying polysilicon load resistor to traverse the severe topography, resulting in an increase in resistor length, while still maintaining the allotted design space, overlying a MOSFET device. The formation of back to back diodes in the polysilicon load resistor also results in an increase in resistance. The back to back diodes are created via N type, ion implantation into only flat regions of an intrinsic, or P type doped, polysilicon load resistor, regions in which the polysilicon load resistor overlaid the flat regions of the underlying raised grid topography, leaving regions of the polysilicon load resistor, located on the sides of the underlying raised grid topography, P type.

Abstract: A method for fabricating polysilicon load resistors, with increased resistance values, for use in SRAM cells, has been developed. An underlying, raised grid topography is used to allow the overlying polysilicon load resistor to traverse the severe topography, resulting in an increase in resistor length, while still maintaining the allotted design space, overlying a MOSFET device. The formation of back to back diodes in the polysilicon load resistor also results in an increase in resistance. The back to back diodes are created via N type, ion implantation into only flat regions of an intrinsic, or P type doped, polysilicon load resistor, regions in which the polysilicon load resistor overlaid the flat regions of the underlying raised grid topography, leaving regions of the polysilicon load resistor, located on the sides of the underlying raised grid topography, P type.