Abstract: A semiconductor structure includes a first device and a second device. The first device includes: a first gate structure formed over an active region and a first air spacer disposed adjacent to the first gate structure. The second device includes: a second gate structure formed over an isolation structure and a second air spacer disposed adjacent to the second gate structure. The first air spacer and the second air spacer have different sizes.

Abstract: A method includes forming a first fin and a second fin protruding from a frontside of a substrate, forming a gate stack over the first and second fins, forming a dielectric feature dividing the gate stack into a first segment engaging the first fin and a second segment engaging the second fin, and growing a first epitaxial feature on the first fin and a second epitaxial feature on the second fin. The dielectric feature is disposed between the first and second epitaxial features. The method also includes performing an etching process on a backside of the substrate to form a backside trench, and forming a backside via in the backside trench. The backside trench exposes the dielectric feature and the first and second epitaxial features. The backside via straddles the dielectric feature and is in electrical connection with the first and second epitaxial features.

Abstract: A docker image is received. The docker image is for a container. The container contains files that allow for virtualization of applications that run within the container. The docker image is parsed to identify layer files in the docker image. Installed software components (e.g., installed files) and/or hardware components in the layer files are identified. Software application index calls are made to generate information that identifies relationships between the installed software components and/or hardware components. The relationships between the installed software components and/or hardware components are then displayed to a user.

Abstract: A gas flow accelerator may include a body portion, and a tapered body portion including a first end integrally formed with the body portion. The gas flow accelerator may include an inlet port connected to the body portion and to receive a process gas to be removed from a semiconductor processing tool by a main pumping line. The semiconductor processing tool may include a chuck and a chuck vacuum line to apply a vacuum to the chuck to retain a semiconductor device. The tapered body portion may be configured to generate a rotational flow of the process gas to prevent buildup of processing byproduct on interior walls of the main pumping line. The gas flow accelerator may include an outlet port integrally formed with a second end of the tapered body portion. An end portion of the chuck vacuum line may be provided through the outlet port.

Abstract: An outlier IC detection method includes acquiring first measured data of a first IC set, training the first measured data for establishing a training model, acquiring second measured data of a second IC set, generating predicted data of the second IC set by using the training model according to the second measured data, generating a bivariate dataset distribution of the second IC set according to the predicted data and the second measured data, acquiring a predetermined Mahalanobis distance on the bivariate dataset distribution of the second IC set, and identifying at least one outlier IC from the second IC set when at least one position of the at least one outlier IC on the bivariate dataset distribution is outside a range of the predetermined Mahalanobis distance.

Abstract: A memory array and an operation method of the memory array are provided. The memory array includes first and second ferroelectric memory devices formed along a gate electrode, a channel layer and a ferroelectric layer between the gate electrode and the channel layer. The ferroelectric memory devices include: a common source/drain electrode and two respective source/drain electrodes, separately in contact with a side of the channel layer opposite to the ferroelectric layer, wherein the common source/drain electrode is disposed between the respective source/drain electrodes; and first and second auxiliary gates, capacitively coupled to the channel layer, wherein the first auxiliary gate is located between the common source/drain electrode and one of the respective source/drain electrodes, and the second auxiliary gate is located between the common source/drain electrode and the other respective source/drain electrode.

Abstract: A system includes a mobile unit, road and procedure pieces, and a controller on the mobile unit that includes an optical sensor, a storage storing instructions and identification lookup tables, and a processor connected to the optical sensor and the storage. The optical sensor scans recognition patterns on the procedure pieces and identification patterns on the road pieces to correspondingly obtain recognition and identification codes. The processor controls the mobile unit to perform actions based on a collection of instructions generated according to the recognition codes and the instruction lookup table and based on entries of coordinate information obtained according to the identification codes and the identification lookup table.

Abstract: A system includes a mobile unit, road and procedure pieces, and a controller on the mobile unit that includes an optical sensor, a storage storing instructions and identification lookup tables, and a processor connected to the optical sensor and the storage. The optical sensor scans recognition patterns on the procedure pieces and identification patterns on the road pieces to correspondingly obtain recognition and identification codes. The processor controls the mobile unit to perform actions based on a collection of instructions generated according to the recognition codes and the instruction lookup table and based on entries of coordinate information obtained according to the identification codes and the identification lookup table.

Abstract: A memory management method and a storage controller are provided. The memory management method includes: dividing a plurality of word lines of a first block into a plurality of word line groups and recording a characteristic value for each of the word line groups; accumulating the characteristic values of a second word line group and a third word line group when reading a first word line group, wherein the second word line group and the third word line group are directly adjacent to the first word line group; and reading the second word line group via a first optimal read voltage group when the characteristic value of the second word line group is greater than a first threshold, wherein the first optimal read voltage group is different from a default read voltage group corresponding to the second word line group.

Abstract: A cosmetic case mirror assembly positioning device includes a mirror frame holder having two spaced lugs raised from one side of an elongate base plate fastened to the top cover of a cosmetic case on the inside, and a mirror frame having two lugs respectively pivoted to either lug on the mirror frame holder and two toothed supports respectively and releasably meshed with the toothed top edge of either lug on the mirror frame holder, and a mirror inserted into a channel on the mirror frame and locked in place by latch pins.