Patents by Inventor Yi-Nan Chen

Yi-Nan Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of forming gate structure
    Patent number: 7094638
    Abstract: A method of forming a gate structure. First, a substrate is provided, and a gate oxide layer, a polysilicon layer, a silicide layer, and a cap layer are consecutively formed onto the substrate. Then, an etching process is performed to etch a portion of the cap layer, the silicide layer, and the polysilicon layer and stop on the polysilicon layer for forming a stacked gate. Thereafter, a portion of the silicide layer exposed on sidewalls of the stacked gate is removed to form a recess. A passivation layer is deposited to fill the recess. The remaining polysilicon layer and the gate oxide layer outside the sidewalls of the stacked gate structure are removed.
    Type: Grant
    Filed: October 17, 2003
    Date of Patent: August 22, 2006
    Assignee: Nanya Technology Corp.
    Inventors: Jin-Tau Huang, Chung-Peng Hao, Yi-Nan Chen, Tse-Yao Huang
  • Method for enhancing adhesion between reworked photoresist and underlying oxynitride film
    Patent number: 7090965
    Abstract: A method for enhancing adhesion between a reworked photoresist and an underlying oxynitride film. A photoresist pattern layer is formed on an oxynitride layer overlying a substrate. The photoresist pattern layer is removed by acidic solution or oxygen-containing plasma. A surface treatment is performed on the oxynitride layer using a development solution to repair the damaged oxynitride layer due to removing the overlying photoresist pattern layer. A reworked photoresist pattern layer is formed on the oxynitride layer.
    Type: Grant
    Filed: July 1, 2003
    Date of Patent: August 15, 2006
    Assignee: Nanya Technology Corporation
    Inventors: Wen-Bin Wu, Yuan-Shan Wu, Yi-Nan Chen, Teng-Yen Huang
  • STI forming method for improving STI step uniformity
    Patent number: 7071075
    Abstract: Disclosed is a shallow trench isolation (STI) forming method for improving STI step uniformity. The method deposits an oxidation layer to a semiconductor structure formed with STIs. After a planarization material layer is formed on the oxidation, then CMP process is performed. By using the method of the present invention, the STI step uniformity can be raised.
    Type: Grant
    Filed: December 8, 2003
    Date of Patent: July 4, 2006
    Assignee: NANYA Technology Corporation
    Inventors: Chung-Peng Hao, Yi-Nan Chen
  • Interconnect structure and method for fabricating the same
    Patent number: 7067418
    Abstract: A method for fabricating interconnects is provided. The method comprises forming a conducting line on a first dielectric layer; forming a first liner layer on the surfaces of the first dielectric layer and the conducting line; forming a second liner layer on the first liner layer; forming a second dielectric layer on the second liner layer, wherein the etching selectivity rate of the second dielectric layer is higher than the etching selectivity rate of the second liner; and patterning the second dielectric layer to form a contact window opening through the second liner layer and the first liner layer to expose the surface of the conducting line. Because the second dielectric layer having an etching rate higher than the etching rate of the second liner layer, the second liner layer can be used as an etch stop layer while patterning the second dielectric layer.
    Type: Grant
    Filed: May 27, 2005
    Date of Patent: June 27, 2006
    Assignee: Nanya Technology Corporation
    Inventors: Tse-Yao Huang, Yi-Nan Chen, Chih-Ching Lin
  • Contact etching utilizing multi-layer hard mask
    Patent number: 7064044
    Abstract: A method for forming contact holes using a multi-layer hard mask. A substrate with a device region and an alignment region having an opening therein to serve as an alignment mark is provided. A dielectric layer is formed overlying the substrate and fills the opening, followed by the multi-layer hard mask. The multi-layer hard mask over the opening is partially removed and that on the device region is patterned to form a plurality of holes therein and expose the underlying dielectric layer. The exposed dielectric layer on the device region is etched to form the plurality of contact holes therein.
    Type: Grant
    Filed: December 21, 2004
    Date of Patent: June 20, 2006
    Assignee: Nanya Technology Corporation
    Inventors: Yi-Nan Chen, Hui-Min Mao
  • Multi-layer hard mask structure for etching deep trench in substrate
    Publication number: 20060127680
    Abstract: A method for etching a deep trench in a substrate. A multi-layer hard mask structure is formed overlying the substrate, which includes a first hard mask layer and at least one second hard mask layer disposed thereon. The first hard mask layer is composed of a first boro-silicate glass (BSG) layer and an overlying first undoped silicon glass (USG) layer and the second is composed of a second BSG layer and an overlying second USG layer. A polysilicon layer is formed overlying the multi-layer hard mask structure and then etched to form an opening therein. The multi-layer hard mask structure and the underlying substrate under the opening are successively etched to simultaneously form the deep trench in the substrate and remove the polysilicon layer. The multi-layer hard mask structure is removed.
    Type: Application
    Filed: February 7, 2006
    Publication date: June 15, 2006
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventors: Kaan-Lu Tzou, Tzu-Ching Tsai, Yi-Nan Chen
  • Method of forming bit line contact via
    Publication number: 20060118886
    Abstract: A method of forming a bit line contact via. The method includes providing a substrate having a transistor with a gate electrode, drain region, and source region, forming a conductive layer overlying the drain region, conformally forming an insulating barrier layer overlying the substrate, blanketly forming a dielectric layer overlying the insulating barrier layer, and forming a via through the dielectric layer and insulating barrier layer, exposing the conductive layer.
    Type: Application
    Filed: January 23, 2006
    Publication date: June 8, 2006
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventors: Tzu-Ching Tsai, Yi-Nan Chen, Hui-Min Mao
  • Deep trench self-alignment process for an active area of a partial vertical cell
    Patent number: 7056832
    Abstract: A deep trench self-alignment process for an active area of a partial vertical cell. A semiconductor substrate with two deep trenches is provided. A deep trench capacitor is formed in each deep trench, and an isolating layer is formed thereon. Each trench is filled with a mask layer. A photoresist layer is formed on the semiconductor substrate between the deep trenches, and the photoresist layer partially covers the mask layer. The semiconductor substrate is etched lower than the isolating layer using the photoresist layer and the mask layer as masks. The photoresist layer and the mask layer are removed, such that the pillar semiconductor substrate between the deep trenches functions as an active area.
    Type: Grant
    Filed: July 18, 2003
    Date of Patent: June 6, 2006
    Assignee: Nanya Technology Corporation
    Inventors: Ming-Cheng Chang, Yi-Nan Chen, Tse-Yao Huang
  • Method for forming bit line
    Patent number: 7052949
    Abstract: A method for forming a bit line. A semiconductor substrate is provided. A MOS having a gate and an S/D area is formed on the semiconductor substrate. A first dielectric layer with a first opening is formed on the semiconductor substrate to expose the S/D area. A conducting layer is formed in the first opening. A barrier layer is formed on the surface of the first dielectric layer and the conducting layer. A second dielectric layer having a second opening and a third opening is formed on the barrier layer, the position of the second opening corresponding to the first opening. Metal layers are formed in the second opening and the third opening as bit lines, respectively.
    Type: Grant
    Filed: June 11, 2003
    Date of Patent: May 30, 2006
    Assignee: Nanya Technology Corporation
    Inventors: Kuo-Chien Wu, Tse-Yao Huang, Yi-Nan Chen
  • Partial vertical memory cell and method of fabricating the same
    Patent number: 7033886
    Abstract: A partial vertical memory cell and fabrication method thereof. A semiconductor substrate is provided, in which two deep trenches having deep trench capacitors respectively are formed, and the deep trench capacitors are lower than a top surface of the semiconductor substrate. A portion of the semiconductor outside the deep trenches is removed to form a pillar between. The pillar is ion implanted to form an ion-doped area in the pillar corner acting as a S/D area. A gate dielectric layer and a conducting layer are conformally formed on the pillar sequentially. An isolation is formed in the semiconductor substrate beside the conducting layer. The conducting layer is defined to form a first gate and a second gate.
    Type: Grant
    Filed: November 26, 2004
    Date of Patent: April 25, 2006
    Assignee: Nanya Technology Corporation
    Inventors: Ming-Cheng Chang, Yi-Chen Chen, Yi-Nan Chen
  • Multi-layer hard mask structure for etching deep trench in substrate
    Patent number: 7029753
    Abstract: A method for etching a deep trench in a substrate. A multi-layer hard mask structure is formed overlying the substrate, which includes a first hard mask layer and at least one second hard mask layer disposed thereon. The first hard mask layer is composed of a first boro-silicate glass (BSG) layer and an overlying first undoped silicon glass (USG) layer and the second is composed of a second BSG layer and an overlying second USG layer. A polysilicon layer is formed overlying the multi-layer hard mask structure and then etched to form an opening therein. The multi-layer hard mask structure and the underlying substrate under the opening are successively etched to simultaneously form the deep trench in the substrate and remove the polysilicon layer. The multi-layer hard mask structure is removed.
    Type: Grant
    Filed: December 4, 2003
    Date of Patent: April 18, 2006
    Assignee: Nanya Technology Corporation
    Inventors: Kaan-Lu Tzou, Tzu-Ching Tsai, Yi-Nan Chen
  • Method of filling bit line contact via
    Patent number: 7026207
    Abstract: A method of filling a bit line contact via. The method includes providing a substrate having a device region and periphery region, the device region having a transistor, having a gate electrode, drain region, and source region, on the substrate, forming a dielectric layer overlying the substrate, the dielectric layer having a bit line contact via exposing the drain region, and periphery contact via exposing the periphery region, forming a doped conductive layer, lower than the dielectric layer, overlying the drain region, conformally forming a barrier layer overlying the dielectric layer, doped conductive layer, and periphery region, and forming a first conductive layer filling the bit line contact via and periphery contact via.
    Type: Grant
    Filed: November 18, 2003
    Date of Patent: April 11, 2006
    Assignee: Nanya Technology Corporation
    Inventors: Tzu-Ching Tsai, Yi-Nan Chen
  • Memory device with vertical transistors and deep trench capacitors and method of fabricating the same
    Patent number: 7009236
    Abstract: A memory device with vertical transistors and deep trench capacitors. The device includes a substrate containing at least one deep trench and a capacitor deposited in the lower portion of the deep trench. A conducting structure, having a first conductive layer and a second conductive layer, is deposited on the trench capacitor. A ring shaped insulator is deposited on the sidewall and between the substrate and the first conductive layer. The first conductive layer is surrounded by the ring shaped insulator, and the second conductive layer is deposited on the first conductive layer and the ring shaped insulator. A diffusion barrier between the second conductive layer and the substrate of the deep trench is deposited on one side of the sidewall of the deep trench. A TTO is deposited on the conducting structure. A control gate is deposited on the TTO.
    Type: Grant
    Filed: October 22, 2003
    Date of Patent: March 7, 2006
    Assignee: Nanya Technology Corporation
    Inventors: Yi-Nan Chen, Hui-Min Mao, Chih-Yuan Hsiao, Ming-Cheng Chang
  • Method for forming contact hole
    Patent number: 7005374
    Abstract: Disclosed is an improved method for forming contact holes. The method of the present invention includes the steps of providing a substrate; forming a plurality of operation layers on the substrate as necessary; forming a poly-silicon layer on the uppermost one of the operation layers; forming an anti-reflective layer on the poly-silicon layer; forming a photoresist layer on the anti-reflective layer to define the positions where the contact holes are to be formed; removing portions of the anti-reflective layer not covered with the photoresist layer; removing the photoresist layer; removing portions of the poly-silicon layer not covered with the anti-reflective layer; and using the residual poly-silicon layer as a mask to etch and form the contact holes.
    Type: Grant
    Filed: December 22, 2003
    Date of Patent: February 28, 2006
    Assignee: Nanya Technology Corporation
    Inventors: Tse-Yao Huang, Yi-Nan Chen
  • Method of reworking layers over substrate
    Patent number: 6998347
    Abstract: A method of reworking an integrated circuit device is described. A substrate having a dielectric layer, a barrier layer, a conductive layer and an anti-reflective layer formed thereon, is provided. The method of reworking the barrier layer, the conductive layer and the anti-reflective layer comprises removing the anti-reflection layer by performing a dry etching process, removing the conductive layer by performing a wet etching process, and then removing the barrier layer by performing a chemical machine polishing process.
    Type: Grant
    Filed: September 17, 2003
    Date of Patent: February 14, 2006
    Assignee: Nanya Technology Corporation
    Inventors: Min-Yi Hsu, Hsin-Jung Ho, Kun-Shin Huang, Yi-Nan Chen, Kaanlu Tzou
  • Interconnect structure and method for fabricating the same
    Patent number: 6992393
    Abstract: A method for fabricating interconnects is provided. The method comprises forming a conducting line on a first dielectric layer; forming a first liner layer on the surfaces of the first dielectric layer and the conducting line; forming a second liner layer on the first liner layer; forming a second dielectric layer on the second liner layer, wherein the etching selectivity rate of the second dielectric layer is higher than the etching selectivity rate of the second liner; and patterning the second dielectric layer to form a contact window opening through the second liner layer and the first liner layer to expose the surface of the conducting line. Because the second dielectric layer having an etching rate higher than the etching rate of the second liner layer, the second liner layer can be used as an etch stop layer while patterning the second dielectric layer.
    Type: Grant
    Filed: March 29, 2004
    Date of Patent: January 31, 2006
    Assignee: Nanya Technology Corp.
    Inventors: Tse-Yao Huang, Yi-Nan Chen, Chih-Ching Lin
  • Contact etching utilizing multi-layer hard mask
    Patent number: 6987322
    Abstract: A method for forming contact holes using a multi-layer hard mask. A substrate with a device region and an alignment region having an opening therein to serve as an alignment mark is provided. A dielectric layer is formed overlying the substrate and fills the opening, followed by the multi-layer hard mask. The multi-layer hard mask over the opening is partially removed and that on the device region is patterned to form a plurality of holes therein and expose the underlying dielectric layer. The exposed dielectric layer on the device region is etched to form the plurality of contact holes therein.
    Type: Grant
    Filed: August 20, 2004
    Date of Patent: January 17, 2006
    Assignee: Nanya Technology Corporation
    Inventors: Yi-Nan Chen, Hui-Min Mao
  • Damascene gate process
    Patent number: 6984566
    Abstract: The invention provides a damascene gate process. A semiconductor substrate having a pad layer and an etch stop layer formed thereon is provided, and an insulating layer is formed to cover the etch stop layer, followed by forming an opening by partially removing the insulating layer, the etch stop layer, and the pad layer. A protective spacer is formed on the sidewall of the opening, wherein the top of the protective spacer is lower than the insulating layer. A gate conducting layer is then formed in the opening. The protective spacer and the insulating layer are removed to expose a portion of the semiconductor substrate and the etch stop layer. Implantation is then performed to form lightly doped drains. A gate spacer is then formed to cover the gate conducting layer. The etch stop layer and the pad layer are removed, and implantation is then performed to a form source/drain.
    Type: Grant
    Filed: November 18, 2003
    Date of Patent: January 10, 2006
    Assignee: Nanya Technology Corporation
    Inventors: Chung-Peng Hao, Yi-Nan Chen
  • Conducting wire and contact opening forming method for reducing photoresist thickness and via resistance
    Patent number: 6979638
    Abstract: Disclosed is a method for forming conducting wire and contact opening in a semiconductor device. The method of the present invention utilizes the formation of metal regions as a mask for etching a conductive layer of the semiconductor device to remove unnecessary portions so as to form conducting wires. The method of the present invention can reduce the necessary thickness of photoresist and well control the via resistance.
    Type: Grant
    Filed: February 23, 2004
    Date of Patent: December 27, 2005
    Assignee: Nanya Technology Corporation
    Inventors: Tse-Yao Huang, Yi-Nan Chen, Chiang-Lin Shih
  • Manufacturing method of a MOSFET gate
    Patent number: 6977134
    Abstract: A manufacturing method for a MOSFET gate structure. The method comprises providing a substrate, sequentially depositing a pad layer and a dielectric layer thereon, defining a gate trench passing through the dielectric layer and the pad layer to expose a predetermined gate area of the substrate, sequentially forming a gate dielectric layer, a first conductive layer, a second conductive layer, and a cap layer on the exposed substrate in the gate trench to form a damascene gate structure, and removing the dielectric layer.
    Type: Grant
    Filed: June 2, 2003
    Date of Patent: December 20, 2005
    Assignee: Nanya Technology Corporation
    Inventors: Chung-Peng Hao, Hui-Min Mao, Yi-Nan Chen, Tzu-Ching Tsai