Abstract: A light-adjusting film is mounted between a color conversion layer and a display panel of a direct type backlight module and has a substrate and at least one light-adjusting layer. The substrate has a central area and a surrounding area. The at least one light-adjusting layer has a pigment and is mounted on the substrate. A content of the pigment is gradually decreased from the surrounding area to the central area. The color of the pigment of the light-adjusting film is a correction color of lights emitted from light emitting surface of the color conversion layer in the backlight module.

Abstract: A light-adjusting film is mounted between a color conversion layer and a display panel of a direct type backlight module and has a substrate and at least one light-adjusting layer. The substrate has a central area and a surrounding area. The at least one light-adjusting layer has a pigment and is mounted on the substrate. A content of the pigment is gradually decreased from the surrounding area to the central area. The color of the pigment of the light-adjusting film is a correction color of lights emitted from light emitting surface of the color conversion layer in the backlight module.

Abstract: A method for fabricating a trench capacitor is disclosed. A substrate having a first pad layer is provided. STI structure is embedded into the first pad layer and the substrate. A second pad layer is deposited over the first pad layer and the STI structure. Two adjacent trenches are etched into the first, second pad layers, and the semiconductor substrate. The second pad layer and a portion of the STI structure between the two trenches are etched to form a ridge. A liner is formed on interior surface of the trenches. A first polysilicon layer is formed on the liner. A capacitor dielectric layer is formed on the first polysilicon layer. The two adjacent trenches are filled with a second polysilicon layer. The second polysilicon layer is then etched until the capacitor dielectric layer is exposed. The fabrication process is easy to integrate to SoC chip.

Abstract: A structure of trench capacitor and method for manufacturing the trench capacitor is provided. The collar oxide layer of the trench capacitor is formed by a thermal oxidation process. Moreover, a protective layer such as silicon nitride covers the collar oxide layer. A failure analysis of the collar oxide layer can be operated by detecting the protective layer. If the protective layer is detected, the collar oxide layer is therefore at a suitable thickness. Furthermore, a mask layer rather than the collar oxide layer is used as a mask during the trench formation.

Abstract: A method for an isolation structure is provided. First, a substrate with a shallow trench isolation is provided. Second, a patterned mask is formed on the substrate. Then, the substrate is etched using the patterned mask to respectively form a first deep trench and a second deep trench as well as a first undercut and a second undercut on opposite sides of the shallow trench isolation. Later, the first deep trench and the second deep trench are partially filled with Si. Afterwards, the first deep trench and the second deep trench are filled with an isolation material to form the isolation structure.

Abstract: A structure of trench capacitor and method for manufacturing the trench capacitor is provided. The collar oxide layer of the trench capacitor is formed by a thermal oxidation process. Moreover, a protective layer such as silicon nitride covers the collar oxide layer. A failure analysis of the collar oxide layer can be operated by detecting the protective layer. If the protective layer is detected, the collar oxide layer is therefore at a suitable thickness. Furthermore, a mask layer rather than the collar oxide layer is used as a mask during the trench formation.

Abstract: A method for an isolation structure is provided. First, a substrate with a shallow trench isolation is provided. Second, a patterned mask is formed on the substrate. Then, the substrate is etched using the patterned mask to respectively form a first deep trench and a second deep trench as well as a first undercut and a second undercut on opposite sides of the shallow trench isolation. Later, the first deep trench and the second deep trench are partially filled with Si. Afterwards, the first deep trench and the second deep trench are filled with an isolation material to form the isolation structure.

Abstract: A method for forming a trench capacitor and memory cell by providing a substrate on which a grid STI and a plurality of active regions covered by a hard mask layer are formed. A photoresist is formed and a low grade photo mask having only X direction consideration is used to define the required pattern on the photoresist. The hard mask layer and the STI are used as an etching mask to etch a plurality of deep trenches. Then diffusion regions, capacitor dielectric layer, and polysilicon filled to form the capacitor bottom electrode are sequentially formed to complete the forming for trench capacitors. After removing the hard mask layer and performing a logic process, the memory cells are completed.

Abstract: A pick-up structure for DRAM capacitors and a DRAM process are described. A substrate with trenches therein is provided, wherein the trenches include a first trench and the sidewall of each of the trenches is formed with a dielectric layer thereon. A conductive layer is formed on the surfaces of the substrate and the trenches, and then a patterned photoresist layer is formed on the conductive layer filling in the trenches and further covering the first trench. The exposed conductive layer is removed to form bottom electrodes in the trenches, and then the patterned photoresist layer is removed. A capacitor dielectric layer is formed on each bottom electrode, and then top electrodes are formed on the substrate filling up the trenches. A contact is then formed on the bottom electrode in the first trench, electrically connecting the substrate via the bottom electrode.

Abstract: A trench capacitor including a substrate, at least a group of capacitor units, an isolation structure and a conductive layer is described. The substrate includes a first trench and a second trench. The group of capacitor units is disposed in the substrate. The group of capacitor units includes a first capacitor disposed in the first trench and a second capacitor disposed in the second trench. The isolation structure is disposed in the substrate between the first capacitor and the second capacitor. The conductive layer is disposed in the substrate above the isolation structure and electrically connected to the first upper electrode and the second upper electrode.

Abstract: A structure of a trench capacitor and method for manufacturing the same. The method includes providing a substrate having a defined memory area and logic area, and performing an STI process to form at least one STI region on the memory area of the substrate and at least one STI region on the logic area of the substrate. Then, a patterned mask is formed on the substrate and the STI region to partially expose the STI region and partially expose the substrate surrounding the STI region. Next, the STI region and the substrate not covered by the mask are etched to from a plurality of deep trench.

Abstract: A method of fabricating a dynamic random access memory is provided. A trench capacitor is formed in a substrate and an isolation structure is formed on the trench capacitor. A gate structure and a passing gate structure are formed on the substrate. The gate structure is on one side of the passing gate structure. A source region and a drain region are formed in the substrate on both sides of the gate structure. A dielectric layer is formed on the substrate. A contact is formed in the dielectric layer and the isolation structure, at the other side of the passing gate structure, and is coupled to the trench capacitor. Since the contact is formed at the other side of the passing gate structure, the contact would not coupled to the source and drain regions when misalignment occurs.

Abstract: Method of manufacturing a trench capacitor includes providing a substrate having a memory array region and a logic region, performing a shallow trench isolation (STI) process for forming at least a STI in the substrate within each of the memory array regions and the logic regions, forming a patterned hard mask and the hard mask exposing a portion of the STI and a portion of the substrate surrounding the STI on the substrate, performing a first etching process to form first deep trenches through the patterned hard mask, performing a second etching process to form second deep trenches extending downwardly from the first deep trenches respectively, and forming a capacitor structure in each of the first deep trenches and the second deep trenches.

Abstract: A method of fabricating trench capacitors is described. A substrate having at least one isolation structure is provided. A first trench and a second trench are formed in the substrate beside the isolation structure. A first lower electrode and a second lower electrode are formed in the substrate around the first trench and the second trench. A first capacitor dielectric layer and a second capacitor dielectric layer are formed on the respective surfaces of the first trench and the second trench. A first upper electrode and a second upper electrode are formed to fill the first trench and the second trench. A portion of the isolation structure between the first trench and the second trench is removed to form an opening. A conductive layer is formed to fill the opening and connect electrically with the first upper electrode and the second upper electrode.

Abstract: A method for fabricating a trench capacitor is disclosed. A substrate having a first pad layer is provided. STI structure is embedded into the first pad layer and the substrate. A second pad layer is deposited over the first pad layer and the STI structure. Two adjacent trenches are etched into the first, second pad layers, and the semiconductor substrate. The second pad layer and a portion of the STI structure between the two trenches are etched to form a ridge. A liner is formed on interior surface of the trenches. A first polysilicon layer is formed on the liner. A capacitor dielectric layer is formed on the first polysilicon layer. The two adjacent trenches are filled with a second polysilicon layer. The second polysilicon layer is then etched until the capacitor dielectric layer is exposed. The fabrication process is easy to integrate to SoC chip.

Abstract: A method for forming a trench capacitor and memory cell by providing a substrate on which a grid STI and a plurality of active regions covered by a hard mask layer are formed. A photoresist is formed and a low grade photo mask having only X direction consideration is used to define the required pattern on the photoresist. The hard mask layer and the STI are used as an etching mask to etch a plurality of deep trenches. Then diffusion regions, capacitor dielectric layer, and polysilicon filled to form the capacitor bottom electrode are sequentially formed to complete the forming for trench capacitors. After removing the hard mask layer and performing a logic process, the memory cells are completed.

Abstract: A method for fabricating a trench capacitor is disclosed. A substrate having a first pad layer is provided. STI structure is embedded into the first pad layer and the substrate. A second pad layer is deposited over the first pad layer and the STI structure. Two adjacent trenches are etched into the first, second pad layers, and the semiconductor substrate. The second pad layer and a portion of the STI structure between the two trenches are etched to form a ridge. A liner is formed on interior surface of the trenches. A first polysilicon layer is formed on the liner. A capacitor dielectric layer is formed on the first polysilicon layer. The two adjacent trenches are filled with a second polysilicon layer. The second polysilicon layer is then etched until the capacitor dielectric layer is exposed. The fabrication process is easy to integrate to SoC chip.

Abstract: A method for forming a trench capacitor and memory cell by providing a substrate on which a grid STI and a plurality of active regions covered by a hard mask layer are formed. A photoresist is formed and a low grade photo mask having only X direction consideration is used to define the required pattern on the photoresist. The hard mask layer and the STI are used as an etching mask to etch a plurality of deep trenches. Then diffusion regions, capacitor dielectric layer, and polysilicon filled to form the capacitor bottom electrode are sequentially formed to complete the forming for trench capacitors. After removing the hard mask layer and performing a logic process, the memory cells are completed.

Abstract: A pick-up structure for DRAM capacitors and a DRAM process are described. A substrate with trenches therein is provided, wherein the trenches include a first trench and the sidewall of each of the trenches is formed with a dielectric layer thereon. A conductive layer is formed on the surfaces of the substrate and the trenches, and then a patterned photoresist layer is formed on the conductive layer filling in the trenches and further covering the first trench. The exposed conductive layer is removed to form bottom electrodes in the trenches, and then the patterned photoresist layer is removed. A capacitor dielectric layer is formed on each bottom electrode, and then top electrodes are formed on the substrate filling up the trenches. A contact is then formed on the bottom electrode in the first trench, electrically connecting the substrate via the bottom electrode.

Abstract: A method for fabricating a trench capacitor is disclosed. A substrate having a first pad layer is provided. STI structure is embedded into the first pad layer and the substrate. A second pad layer is deposited over the first pad layer and the STI structure. Two adjacent trenches are etched into the first, second pad layers, and the semiconductor substrate. The second pad layer and a portion of the STI structure between the two trenches are etched to form a ridge. A liner is formed on interior surface of the trenches. A first polysilicon layer is formed on the liner. A capacitor dielectric layer is formed on the first polysilicon layer. The two adjacent trenches are filled with a second polysilicon layer. The second polysilicon layer is then etched until the capacitor dielectric layer is exposed. The fabrication process is easy to integrate to SoC chip.