Patents by Inventor Yi-Ning He

Yi-Ning He has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9343567
    Abstract: A semiconductor device is includes a substrate, a gate positioned on the substrate, and a drain region and a source region formed at two respective sides of the gate in the substrate. The drain region includes a first doped region having a first conductivity type, a second doped region having a second conductivity type, and a third doped region. The first conductivity type and the second conductivity type are complementary to each other. The semiconductor device further includes a first well region formed under the first doped region, a second well region formed under the second doped region, and a third well region formed under the third doped region. The first well region, the second well region, and the third well region all include the first conductivity type. A concentration of the second well region is different from a concentration of the third well region.
    Type: Grant
    Filed: August 8, 2014
    Date of Patent: May 17, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Ning He, Jhih-Ming Wang, Lu-An Chen, Tien-Hao Tang, Kuan-Cheng Su
  • Publication number: 20160043216
    Abstract: A semiconductor device is includes a substrate, a gate positioned on the substrate, and a drain region and a source region formed at two respective sides of the gate in the substrate. The drain region includes a first doped region having a first conductivity type, a second doped region having a second conductivity type, and a third doped region. The first conductivity type and the second conductivity type are complementary to each other. The semiconductor device further includes a first well region formed under the first doped region, a second well region formed under the second doped region, and a third well region formed under the third doped region. The first well region, the second well region, and the third well region all include the first conductivity type. A concentration of the second well region is different from a concentration of the third well region.
    Type: Application
    Filed: August 8, 2014
    Publication date: February 11, 2016
    Inventors: Yi-Ning He, Jhih-Ming Wang, Lu-An Chen, Tien-Hao Tang, Kuan-Cheng Su
  • Patent number: 9142540
    Abstract: A semiconductor device includes a substrate, a gate positioned on the substrate, a drain and a source formed in the substrate at respective two sides of the gate, and a doped region formed in the source. The drain and the source comprise a first conductivity type and the doped region comprises a second conductivity type. The first conductivity type and the second conductivity type are complementary to each other.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: September 22, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Ning He, Lu-An Chen, Tien-Hao Tang
  • Publication number: 20140319613
    Abstract: A semiconductor device includes a substrate, a gate positioned on the substrate, a drain and a source formed in the substrate at respective two sides of the gate, and a doped region formed in the source. The drain and the source comprise a first conductivity type and the doped region comprises a second conductivity type. The first conductivity type and the second conductivity type are complementary to each other.
    Type: Application
    Filed: April 30, 2013
    Publication date: October 30, 2014
    Applicant: United Microelectronics Corp.
    Inventors: Yi-Ning He, Lu-An Chen, Tien-Hao Tang