Patents by Inventor Yi-Pei SU

Yi-Pei SU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Phase-locked loop circuit with improved performance
    Patent number: 9294104
    Abstract: A phase-locked loop circuit includes a phase detector, a charge pump, a capacitor, and a capacitor multiplier. The phase detector receives a reference frequency and a feedback frequency to generate a up/down signal. The charge pump, which includes a positive node and a negative node, receives the up/down signal to generate a first current. The capacitor is coupled to the negative node. The capacitor multiplier, coupled to the negative node, generates a second current which is the first current divided by a first scaling number.
    Type: Grant
    Filed: July 16, 2014
    Date of Patent: March 22, 2016
    Assignee: Intel Corporation
    Inventors: Shih-An Yu, Sen-You Liu, Fang-Ren Liao, Yi-Pei Su
  • PHASE-LOCKED LOOP CIRCUIT WITH IMPROVED PERFORMANCE
    Publication number: 20160020773
    Abstract: A phase-locked loop circuit includes a phase detector, a charge pump, a capacitor, and a capacitor multiplier. The phase detector receives a reference frequency and a feedback frequency to generate a up/down signal. The charge pump, which includes a positive node and a negative node, receives the up/down signal to generate a first current. The capacitor is coupled to the negative node. The capacitor multiplier, coupled to the negative node, generates a second current which is the first current divided by a first scaling number.
    Type: Application
    Filed: July 16, 2014
    Publication date: January 21, 2016
    Inventors: Shih-An YU, Sen-You LIU, Fang-Ren LIAO, Yi-Pei SU