Abstract: The present application provides a memory cell and a method for manufacturing the same. The memory cell comprises an interfacial capping layer, wherein the interfacial capping layer comprises a first interface layer composed of tungsten nitride and a second interface layer composed of tungsten carbonitride. The first interface layer provides interface tensile tension, which increases the polarization degree of the memory cell. The second interface layer blocks oxygen ions, prevents the first interface layer from being oxidized, and further prevents the top electrode of the memory cell from being oxidized, thereby improving the durability of the memory cell. In addition, the present application further optimizes the annealing process, places the memory cell in the middle of a high-temperature furnace for annealing and heating, and sets a plurality of protection wafers before and after the memory cell to protect the memory cell from stress.

Abstract: A chip package includes a chip, an insulating layer and a conductive layer. The chip includes a substrate, an epitaxy layer, a device region and a conductive pad. The epitaxy layer is disposed on the substrate, and the device region and the conductive pad are disposed on the epitaxy layer. The conductive pad is at a side of the device region and connected to the device region. The conductive pad protrudes out of a side surface of the epitaxy layer. The insulating layer is disposed below the substrate and extended to cover the side surface of the epitaxy layer. The conductive layer is disposed below the insulating layer and extended to contact the conductive pad. The conductive layer and the side surface of the epitaxy layer are separated by a first distance.

Abstract: A chip package includes a chip, an insulating layer and a conductive layer. The chip includes a substrate, an epitaxy layer, a device region and a conductive pad. The epitaxy layer is disposed on the substrate, and the device region and the conductive pad are disposed on the epitaxy layer. The conductive pad is at a side of the device region and connected to the device region. The conductive pad protrudes out of a side surface of the epitaxy layer. The insulating layer is disposed below the substrate and extended to cover the side surface of the epitaxy layer. The conductive layer is disposed below the insulating layer and extended to contact the conductive pad. The conductive layer and the side surface of the epitaxy layer are separated by a first distance.

Abstract: A synchronous rectifying buck-boost converter includes a controller, first and second transistors, an inductor and a capacitor. The controller is connected to the gates of the first and second transistors for controlling ON/OFF of the first and second transistors, and further controls the current of the inductor and charge/discharge of the capacitor. The first and second transistors connected in series are connected to the controller and the inductor. The inductor is connected to a first external power unit or a first external loading device. The drain of the first transistor is connected to a second external power unit or a second external loading device such that a low-voltage input power of the first external power unit is converted to a high-voltage output power or a high-voltage input power of the second external power unit is converted to a low-voltage output power.

Abstract: A digital pulse width modulation controller includes a pulse width modulation controller, a selection unit having at least one selector, a comparison unit having at least one comparator, and a signal conversion unit having at least one digital-to-analog converter. The digital-to-analog converter generates a reference current and/or voltage. The comparator receives the reference current and/or voltage, and performs a comparison operation to generate a comparison signal based on a feedback signal. The selector selects one selection signal to input into the pulse width modulation controller, which receives other parameters set by a user or the system at the same time so as to control characteristics of the digital pulse width modulation signals, thereby improving the electric properties of a loading circuit.

Abstract: A digital pulse width modulation controller includes a pulse width modulation controller, a selection unit having at least one selector, a comparison unit having at least one comparator, and a signal conversion unit having at least one digital-to-analog converter. The digital-to-analog converter generates a reference current and/or voltage. The comparator receives the reference current and/or voltage, and performs a comparison operation to generate a comparison signal based on a feedback signal. The selector selects one selection signal to input into the pulse width modulation controller, which receives other parameters set by a user or the system at the same time so as to control characteristics of the digital pulse width modulation signals, thereby improving the electric properties of a loading circuit.

Abstract: A synchronous rectifying buck-boost converter includes a controller, first and second transistors, an inductor and a capacitor. The controller is connected to the gates of the first and second transistors for controlling ON/OFF of the first and second transistors, and further controls the current of the inductor and charge/discharge of the capacitor. The first and second transistors connected in series are connected to the controller and the inductor. The inductor is connected to a first external power unit or a first external loading device. The drain of the first transistor is connected to a second external power unit or a second external loading device such that a low-voltage input power of the first external power unit is converted to a high-voltage output power or a high-voltage input power of the second external power unit is converted to a low-voltage output power.