Patents by Inventor Yi-Pin Lin
Yi-Pin Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 12177964Abstract: A circuit board includes a first substrate, a second substrate, a third substrate, a plurality of conductive structures and a conductive via structure. The second substrate is disposed between the first substrate and the third substrate. The third substrate has an opening and includes a first dielectric layer, a second dielectric layer, and a third dielectric layer. The opening penetrates the first dielectric layer and the second dielectric layer, and the third dielectric layer fully fills the opening. The conductive via structure penetrates the first substrate, the second substrate, the third dielectric layer of the third substrate, and is electrically connected to the first substrate and the third substrate to define a signal path. The first substrate, the second substrate, and the third substrate are electrically connected through the conductive structures to define a ground path, and the ground path surrounds the signal path.Type: GrantFiled: April 1, 2022Date of Patent: December 24, 2024Assignee: Unimicron Technology Corp.Inventors: Jun-Rui Huang, Chih-Chiang Lu, Yi-Pin Lin, Ching-Sheng Chen
-
Patent number: 12170331Abstract: A titanium precursor is used to selectively form a titanium silicide (TiSix) layer in a semiconductor device. A plasma-based deposition operation is performed in which the titanium precursor is provided into an opening, and a reactant gas and a plasma are used to cause silicon to diffuse to a top surface of a transistor structure. The diffusion of silicon results in the formation of a silicon-rich surface of the transistor structure, which increases the selectivity of the titanium silicide formation relative to other materials of the semiconductor device. The titanium precursor reacts with the silicon-rich surface to form the titanium silicide layer. The selective titanium silicide layer formation results in the formation of a titanium silicon nitride (TiSixNy) on the sidewalls in the opening, which enables a conductive structure such as a metal source/drain contact to be formed in the opening without the addition of another barrier layer.Type: GrantFiled: February 16, 2022Date of Patent: December 17, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Wei Chang, Chia-Hung Chu, Hsu-Kai Chang, Sung-Li Wang, Kuan-Kan Hu, Shuen-Shin Liang, Kao-Feng Lin, Hung Pin Lu, Yi-Ying Liu, Chuan-Hui Shen
-
Publication number: 20240398878Abstract: A method for preventing a severe acute respiratory syndrome coronavirus 2 (SARS-CoV-2) infection-associated disorder includes use of a composition containing live Bacillus coagulans CB85 which is deposited under the Budapest Treaty at the Deutsche Sammlung von Mikroorganismen und Zellkulturen (DSMZ) GmbH under an accession number DSM 33893, and heat-killed Lactobacillus plantarum CB102 which is deposited under the Budapest Treaty at the DSMZ GmbH under an accession number DSM 33894.Type: ApplicationFiled: November 1, 2023Publication date: December 5, 2024Inventors: Meei-Yn LIN, Hung-Pin CHIU, Yi-Heng CHIU
-
Patent number: 12144113Abstract: A circuit board structure includes a substrate, a first build-up structure layer, first and second external circuit layers, at least one first conductive via, and second conductive vias. The first build-up structure layer is disposed on a first circuit layer of the substrate. The first external circuit layer is disposed on the first build-up structure layer. The second external circuit layer is disposed on a second circuit layer and a portion of a third dielectric layer of the substrate. The first conductive via is electrically connected to the first external circuit layer and the second external circuit layer to define a signal path. The second conductive vias surround the first conductive via, and the first external circuit layer, the second conductive vias, the first circuit layer, the outer conductive layer, and the second external circuit layer define a first ground path. The first ground path surrounds the signal path.Type: GrantFiled: September 7, 2022Date of Patent: November 12, 2024Assignee: Unimicron Technology Corp.Inventors: Chih-Chiang Lu, Chi-Min Chang, Ming-Hao Wu, Yi-Pin Lin, Tung-Chang Lin, Jun-Rui Huang
-
Publication number: 20240371980Abstract: A method for making a semiconductor device includes: forming a first gate stack over a first fin; forming a first gate spacer extending along a side of the first gate stack; forming a second gate spacer over the first gate spacer; forming a third gate spacer over the second gate spacer, the third gate spacer; forming a source/drain region adjacent the third gate spacer; depositing an interlayer dielectric (ILD) over the source/drain region, the ILD including a third dielectric material; and removing at least a portion of the second gate spacer to form a void, while exposing a top surface of the ILD. The void includes a vertical portion extending between the first gate spacer and the source/drain region, and between the first gate spacer and the ILD. The void includes a horizontal portion extending beneath the source/drain region.Type: ApplicationFiled: July 17, 2024Publication date: November 7, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsu Ming Hsiao, Ming-Jhe Sie, Hsiu-Hao Tsao, Hong Pin Lin, Che-fu Chen, An Chyi Wei, Yi-Jen Chen
-
Patent number: 12121920Abstract: A microstructured passage module for aerosolizer is disclosed. The module includes a plate overlaid by a cover, an entrance, an exit, a plurality of protrusions and a plurality of pillars. The protrusions and pillars project from and are integral parts of the plate. Further, the plate can be divided into a first zone proximate to the entrance and a second zone proximate to the exit. The protrusions are arranged into parallel rows in a direction from the entrance to the exit and form parallel passages therebetween in the first zone for the liquid to flow along. The protrusions in each column are spaced from one another by tunnels. The pillars are interposingly disposed in the second zone and define certain channels therebetween. Moreover, a plurality of pillars further disposed in the passages increase a flow resistance for the liquid flowing through the passages.Type: GrantFiled: November 6, 2017Date of Patent: October 22, 2024Assignee: MICROBASE TECHNOLOGY CORP.Inventors: Shu-Pin Hsieh, Yi-Tong Chen, Yi-Ting Lin, Po-Chuan Chen
-
Patent number: 12115215Abstract: Provided is an immunogenic composition including a peptide, wherein consecutive amino acids of the peptide include at least amino acids of SEQ ID NO:1 and one or more adjuvants. Also provided is a method of vaccinating a subject against Borrelia burgdorferi, including administering to the subject an effective amount of the immunogenic composition.Type: GrantFiled: August 17, 2023Date of Patent: October 15, 2024Assignee: Health Research, Inc.Inventors: Yi-Pin Lin, Kaspars Tars
-
Patent number: 12090182Abstract: Disclosed herein is a method for preventing or alleviating particulate matter-induced lung injury. The method includes administering to a subject in need thereof a pharmaceutical composition including at least one heat-killed lactic acid bacterial strain that is selected from the group consisting of Lactobacillus plantarum CB102 which is deposited at the Deutsche Sammlung von Mikroorganismen und Zellkulturen (DSMZ) GmbH under an accession number DSM 33894, Lactobacillus acidophilus JCM 1132, Bifidobacterium longum CB108 which is deposited at the DSMZ GmbH under an accession number DSM 33895, Bifidobacterium animalis subsp. lactis JCM 10602, and combinations thereof.Type: GrantFiled: November 18, 2021Date of Patent: September 17, 2024Assignee: CHAMBIO CO., LTD.Inventors: Meei-Yn Lin, Hung-Pin Chiu, Yi-Heng Chiu
-
Patent number: 12068398Abstract: A method, for making a semiconductor device, includes forming a first fin over a substrate. The method includes forming a dummy gate stack on the first fin. The method includes forming a first gate spacer along a side of the dummy gate stack. The first gate spacer includes a first dielectric material. The method includes forming a second gate spacer along a side of the first gate spacer. The second gate spacer includes a semiconductor material. The method includes forming a source/drain region in the first fin adjacent the second gate spacer. The method includes removing at least a portion of the second gate spacer to form a void extending between the first gate spacer and the source/drain region.Type: GrantFiled: April 25, 2023Date of Patent: August 20, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsu Ming Hsiao, Ming-Jhe Sie, Hsiu-Hao Tsao, Hong Pin Lin, Che-fu Chen, An Chyi Wei, Yi-Jen Chen
-
Publication number: 20240207382Abstract: Provided is an immunogenic composition including a peptide, wherein consecutive amino acids of the peptide include at least amino acids 186-193 of SEQ ID NO:1 and one or more adjuvants. In an example, the peptide is covalently linked to an amino acid sequence including SEQ ID NO:2.Type: ApplicationFiled: August 17, 2023Publication date: June 27, 2024Applicants: Health Research, Inc., Latvian Biomedical Research and Study CenterInventors: Yi-Pin LIN, Kaspars TARS
-
Patent number: 11989005Abstract: A system performs adaptive thermal ceiling control at runtime. The system includes computing circuits and a thermal management module. When detecting a runtime condition change that affects power consumption in the system, the thermal management module determines an adjustment to the thermal ceiling of a computing circuit, and increases the thermal ceiling of the computing circuit according to the adjustment.Type: GrantFiled: September 30, 2021Date of Patent: May 21, 2024Assignee: MediaTek Inc.Inventors: Bo-Jr Huang, Jia-Wei Fang, Jia-Ming Chen, Ya-Ting Chang, Chien-Yuan Lai, Cheng-Yuh Wu, Yi-Pin Lin, Wen-Wen Hsieh, Min-Shu Wang
-
Patent number: 11895772Abstract: An interlayer connective structure is suitable for being formed in a wiring board, in which the wiring board includes two traces and an insulation part between the traces. The insulation part has a through hole. The interlayer connective structure located in the through hole is connected to the traces. The interlayer connective structure includes a column and a pair of protuberant parts. The protuberant parts are located at two ends of the through hole respectively and connected to the column and the traces. The protuberant parts stick out from the outer surfaces of the traces respectively. Each of the protuberant parts has a convex curved surface, in which the distance between the convex curved surface and the axis of the through hole is less than the radius of the through hole.Type: GrantFiled: July 15, 2021Date of Patent: February 6, 2024Assignee: Unimicron Technology Corp.Inventors: Chi-Min Chang, Ching-Sheng Chen, Jun-Rui Huang, Wei-Yu Liao, Yi-Pin Lin
-
Patent number: 11792918Abstract: A co-axial structure includes a substrate, a first conductive structure, a second conductive structure, and an insulating layer. The substrate includes a first surface. The first conductive structure includes a first circuit deposited on the first surface and a first via penetrating the substrate. The second conductive structure includes a second circuit deposited on the first surface and a second via penetrating the substrate. The first via and the second via extend along a first direction. The first circuit and the second circuit extend along a second direction, and the second direction is perpendicular to the first direction. The insulating layer is located between the first via and the second via. The insulating layer includes a filler. The first conductive structure and the second conductive structure are electrically insulated. The first circuit and the second circuit are coplanar.Type: GrantFiled: November 21, 2021Date of Patent: October 17, 2023Assignee: Unimicron Technology Corp.Inventors: Pei-Wei Wang, Heng-Ming Nien, Ching-Sheng Chen, Yi-Pin Lin, Shih-Liang Cheng
-
Patent number: 11771750Abstract: Provided is an immunogenic composition including a peptide, wherein consecutive amino acids of the peptide include at least amino acids 186-193 of SEQ ID NO:1 and one or more adjuvants. In an example, the peptide is covalently linked to an amino acid sequence including SEQ ID NO:2. Also provided is a method of vaccinating a subject against Borrelia burgdorferi, including administering to the subject an effective amount of the immunogenic composition.Type: GrantFiled: March 28, 2022Date of Patent: October 3, 2023Assignees: HEALTH RESEARCH, INC., LATVIAN BIOMEDICAL RESEARCH AND STUDY CENTERInventors: Yi-Pin Lin, Kaspars Tars
-
Publication number: 20230262890Abstract: A circuit board structure includes a substrate, a first build-up structure layer, first and second external circuit layers, at least one first conductive via, and second conductive vias. The first build-up structure layer is disposed on a first circuit layer of the substrate. The first external circuit layer is disposed on the first build-up structure layer. The second external circuit layer is disposed on a second circuit layer and a portion of a third dielectric layer of the substrate. The first conductive via is electrically connected to the first external circuit layer and the second external circuit layer to define a signal path. The second conductive vias surround the first conductive via, and the first external circuit layer, the second conductive vias, the first circuit layer, the outer conductive layer, and the second external circuit layer define a first ground path. The first ground path surrounds the signal path.Type: ApplicationFiled: September 7, 2022Publication date: August 17, 2023Applicant: Unimicron Technology Corp.Inventors: Chih-Chiang Lu, Chi-Min Chang, Ming-Hao Wu, Yi-Pin Lin, Tung-Chang Lin, Jun-Rui Huang
-
Publication number: 20230262893Abstract: A circuit board, including a first dielectric material, a second dielectric material, a third dielectric material, a fourth dielectric material, a first external circuit layer, a second external circuit layer, a conductive structure, a first conductive via, and multiple second conductive vias, is provided. The first conductive via at least passes through the first dielectric material and the fourth dielectric material, and is electrically connected to the first external circuit layer and the second external circuit layer to define a signal path. The second conductive vias pass through the first dielectric material, the second dielectric material, the third dielectric material, and a part of the conductive structure, and surround the first conductive via. The second conductive vias are electrically connected to the first external circuit layer, the conductive structure, and the second external circuit layer to define a ground path, and the ground path surrounds the signal path.Type: ApplicationFiled: August 23, 2022Publication date: August 17, 2023Applicant: Unimicron Technology Corp.Inventors: Chih-Chiang Lu, Jun-Rui Huang, Ming-Hao Wu, Yi-Pin Lin, Tung-Chang Lin
-
Publication number: 20230114681Abstract: Systems, devices, apparatuses, components, methods, and techniques for media a simple user interface that can facilitate discovery of contextually relevant media content with minimal navigation are provided. For example, the disclosed user interface may present contextually relevant categories, sub-categories and media content items while concurrently playing a media content item predicted to likely be selected by the user.Type: ApplicationFiled: October 8, 2021Publication date: April 13, 2023Applicant: Spotify ABInventors: Achal Varma, Arjun Shantanu Narayen, Katherine Yi-Pin Lin, Björn Håkan Lindberg, Jason Allen Russell
-
Publication number: 20220386460Abstract: An interlayer connective structure is suitable for being formed in a wiring board, in which the wiring board includes two traces and an insulation part between the traces. The insulation part has a through hole. The interlayer connective structure located in the through hole is connected to the traces. The interlayer connective structure includes a column and a pair of protuberant parts. The protuberant parts are located at two ends of the through hole respectively and connected to the column and the traces. The protuberant parts stick out from the outer surfaces of the traces respectively. Each of the protuberant parts has a convex curved surface, in which the distance between the convex curved surface and the axis of the through hole is less than the radius of the through hole.Type: ApplicationFiled: July 15, 2021Publication date: December 1, 2022Inventors: Chi-Min CHANG, Ching-Sheng CHEN, Jun-Rui HUANG, Wei-Yu LIAO, Yi-Pin LIN
-
Publication number: 20220334558Abstract: A system performs adaptive thermal ceiling control at runtime. The system includes computing circuits and a thermal management module. When detecting a runtime condition change that affects power consumption in the system, the thermal management module determines an adjustment to the thermal ceiling of a computing circuit, and increases the thermal ceiling of the computing circuit according to the adjustment.Type: ApplicationFiled: September 30, 2021Publication date: October 20, 2022Inventors: Bo-Jr Huang, Jia-Wei Fang, Jia-Ming Chen, Ya-Ting Chang, Chien-Yuan Lai, Cheng-Yuh Wu, Yi-Pin Lin, Wen-Wen Hsieh, Min-Shu Wang
-
Patent number: D1044812Type: GrantFiled: December 21, 2021Date of Patent: October 1, 2024Assignee: Sunrex Technology Corp.Inventors: Shih-Pin Lin, Chun-Chieh Chen, Yi-Wen Tsai, Ling-Cheng Tseng, Ching-Yao Huang, Yu-Shuo Yang, Yu-Xiang Geng, Cheng-Yu Chuang, Chi-Shu Hsu