Abstract: Embodiment methods for performing a high pressure anneal process during the formation of a semiconductor device, and embodiment devices therefor, are provided. The high pressure anneal process may be a dry high pressure anneal process in which a pressurized environment of the anneal includes one or more process gases. The high pressure anneal process may be a wet anneal process in which a pressurized environment of the anneal includes steam.

Abstract: A semiconductor device includes a bottom wafer, a top wafer bonded to the bottom wafer, a first dielectric layer, a second dielectric layer, a deep via conductor structure, and a connection pad. The top wafer includes a first interconnection structure. The first dielectric layer is disposed on the top wafer. The second dielectric layer is disposed on the first dielectric layer. The deep via conductor structure penetrates through the second dielectric layer and the first dielectric layer and is connected with the first interconnection structure. The connection pad is disposed on the second dielectric layer and the deep via conductor structure. A first portion of the second dielectric layer is sandwiched between the connection pad and the first dielectric layer. A second portion of the second dielectric layer is connected with the first portion, and a thickness of the second portion is less than a thickness of the first portion.

Abstract: A method for fabricating a semiconductor device includes the steps of first bonding a top wafer to a bottom wafer, in which the top wafer has a first metal interconnection including a first barrier layer exposing from a bottom surface of the top wafer. Next, a dielectric layer is formed on the bottom surface of the top wafer and then a second metal interconnection is formed in the dielectric layer and connected to the first metal interconnection, in which the second metal interconnection includes a second barrier layer and the first barrier layer and the second barrier layer include a H-shape altogether.

Abstract: A memory with built-in synchronous-write-through (SWT) redundancy includes a plurality of memory input/output (IO) arrays, a plurality of SWT circuits, and at least one spare SWT circuit. The at least one spare SWT circuit is used to replace at least one of the plurality of SWT circuits that is defective.

Abstract: The invention provides a method and associated processor for improving software execution of an electronic device. The method may comprise: by a processor of the electronic device, identifying whether a target program is classified, according to whether the target program relates to an user interface of the electronic device, as one of suppressible programs; and, based on whether at least one suppression condition is satisfied, performing at least one suppressing operation on one or more of the suppressible programs.

Abstract: An input method includes following steps: recording a single-stroke input, converting the recorded single-stroke input into a vector combination defined by one or more pre-defined vectors, and performing user input recognition according to the vector combination. The vector based recognition scheme using certain distinguishable vectors may offer a higher recognition rate and/or a lower misjudgment rate. Moreover, since one user input may be immediately recognized at the end of one single-stroke input, the response time can be reduced to enhance the user experience.