Abstract: A memory with built-in bypass redundancy includes a plurality of memory input/output (IO) arrays, a plurality of bypass circuits, and at least one spare bypass circuit. Each of the bypass circuits and the spare bypass circuit is used to provide a bypass path for bypassing a memory input to a memory output. The at least one spare bypass circuit is used to replace at least one of the plurality of bypass circuits that is defective.

Abstract: A memory with built-in synchronous-write-through (SWT) redundancy includes a plurality of memory input/output (IO) arrays, a plurality of SWT circuits, and at least one spare SWT circuit. The at least one spare SWT circuit is used to replace at least one of the plurality of SWT circuits that is defective.

Abstract: A memory with built-in synchronous-write-through (SWT) redundancy includes a plurality of memory input/output (IO) arrays, a plurality of SWT circuits, and at least one spare SWT circuit. The at least one spare SWT circuit is used to replace at least one of the plurality of SWT circuits that is defective.

Abstract: The present invention provides a pseudo dual-port memory. The pseudo dual-port memory includes a single-port memory, a multiplexer, a timing control circuit and an output circuit. The multiplexer is configured to sequentially output a first address and a second address to the single-port memory. The output circuit is configured to receive output data from the single-port memory to generate a first reading result corresponding to the first address and a second reading result corresponding to the second address. The output circuit includes a first sense amplifier and a second sense amplifier, wherein the first sense amplifier receives the output data to generate first data serving as the first reading result according to a first control signal, and the second sense amplifier receives the output data to generate second data serving as the second reading result according to a second control signal.

Abstract: A self-repair memory circuit includes a cell array, a controller, a row repair decoder, and a column repair decoder. The cell array includes rows and columns of memory cells. The controller receives an input indicating row repair or column repair, and a repair address shared by the row repair and the column repair of the cell array. The row repair decoder maps the repair address of a defective row to a redundant row of the cell array when the input indicates the row repair. The column repair decoder maps the repair address of a defective column to another column of the cell array when the input indicates the column repair.

Abstract: The present invention provides a pseudo dual-port memory. The pseudo dual-port memory includes a single-port memory, a multiplexer, a timing control circuit and an output circuit. The multiplexer is configured to sequentially output a first address and a second address to the single-port memory. The output circuit is configured to receive output data from the single-port memory to generate a first reading result corresponding to the first address and a second reading result corresponding to the second address. The output circuit includes a first sense amplifier and a second sense amplifier, wherein the first sense amplifier receives the output data to generate first data serving as the first reading result according to a first control signal, and the second sense amplifier receives the output data to generate second data serving as the second reading result according to a second control signal.

Abstract: The present invention provides a pseudo dual-port memory. The pseudo dual-port memory includes a single-port memory, a multiplexer, a timing control circuit and an output circuit. The multiplexer is configured to sequentially output a first address and a second address to the single-port memory. The output circuit is configured to receive output data from the single-port memory to generate a first reading result corresponding to the first address and a second reading result corresponding to the second address. The output circuit includes a first sense amplifier and a second sense amplifier, wherein the first sense amplifier receives the output data to generate first data serving as the first reading result according to a first control signal, and the second sense amplifier receives the output data to generate second data serving as the second reading result according to a second control signal.

Abstract: A self-repair memory circuit includes a cell array, a controller, a row repair decoder, and a column repair decoder. The cell array includes rows and columns of memory cells. The controller receives an input indicating row repair or column repair, and a repair address shared by the row repair and the column repair of the cell array. The row repair decoder maps the repair address of a defective row to a redundant row of the cell array when the input indicates the row repair. The column repair decoder maps the repair address of a defective column to another column of the cell array when the input indicates the column repair.

Abstract: The present invention provides a pseudo dual-port memory. The pseudo dual-port memory includes a single-port memory, a multiplexer, a timing control circuit and an output circuit. The multiplexer is configured to sequentially output a first address and a second address to the single-port memory. The output circuit is configured to receive output data from the single-port memory to generate a first reading result corresponding to the first address and a second reading result corresponding to the second address. The output circuit includes a first sense amplifier and a second sense amplifier, wherein the first sense amplifier receives the output data to generate first data serving as the first reading result according to a first control signal, and the second sense amplifier receives the output data to generate second data serving as the second reading result according to a second control signal.

Abstract: A pre-processing circuit is used for pre-processing a data-line voltage representative of a data output of a memory device. The pre-processing circuit includes a pre-charging circuit and a clamping circuit. The pre-charging circuit pre-charges a data line to adjust the data-line voltage at the data line that is coupled to the memory device. The clamping circuit clamps the data-line voltage to generate a clamped data-line voltage when the data-line voltage is pre-charged to a level that enables a clamping function of the clamping circuit, wherein the clamped data-line voltage is lower than a supply voltage of the pre-processing circuit. The clamping circuit includes a feedback circuit that feeds back a control voltage according to the data-line voltage at the data line, and further reduces its direct current (DC) leakage when the data-line voltage is clamped, wherein the clamping function of the clamping circuit is controlled by the control voltage.

Abstract: A pre-processing circuit is used for pre-processing a data-line voltage representative of a data output of a memory device. The pre-processing circuit includes a pre-charging circuit and a clamping circuit. The pre-charging circuit pre-charges a data line to adjust the data-line voltage at the data line that is coupled to the memory device. The clamping circuit clamps the data-line voltage to generate a clamped data-line voltage when the data-line voltage is pre-charged to a level that enables a clamping function of the clamping circuit, wherein the clamped data-line voltage is lower than a supply voltage of the pre-processing circuit. The clamping circuit includes a feedback circuit that feeds back a control voltage according to the data-line voltage at the data line, and further reduces its direct current (DC) leakage when the data-line voltage is clamped, wherein the clamping function of the clamping circuit is controlled by the control voltage.