Abstract: An optimization method, an optimization system for computer programming code and an electronic device using the same are provided. The optimization method includes the following steps. Several optimizers each having several branch paths are provided. A counter is set on each of the branch paths. When the optimizers run through the branch paths, the counters set on the branch paths, where the optimizer run through, are counted. The computer programming code is compiled through the optimizers. Several count values of the counters are obtained. The count values are collected to obtain a feature vector of the computer programming code. The feature vector is inputted to a machine learning model to obtain an optimizer collection suitable for the computer programming code.

Abstract: A variable inference system and a variable inference method for a software program are provided. The variable inference system and method calculate a first variable type output corresponding to an unknown variable for a plurality of first basic blocks of a software program. The variable inference system and method calculate a second variable type input corresponding to the unknown variable for a second basic block of the software program. The variable inference system and method calculate a second variable type generation when the second basic block includes a primitive instruction corresponding to the unknown variable. The variable inference system and method calculate a second variable type kill. The variable inference system and method calculate a second variable output corresponding to the unknown variable for the second basic block according to the second variable type input, the second variable type generation and the second variable type kill.

Abstract: A variable inference system and a variable inference method for a software program are provided. The variable inference system and method calculate a first variable type output corresponding to an unknown variable for a plurality of first basic blocks of a software program. The variable inference system and method calculate a second variable type input corresponding to the unknown variable for a second basic block of the software program. The variable inference system and method calculate a second variable type generation when the second basic block includes a primitive instruction corresponding to the unknown variable. The variable inference system and method calculate a second variable type kill. The variable inference system and method calculate a second variable output corresponding to the unknown variable for the second basic block according to the second variable type input, the second variable type generation and the second variable type kill.

Abstract: An exemplary embodiment of the present disclosure illustrates a hybrid dynamic code compiling device having a parser, a native code generator, and a dynamic code rewriter, wherein the parser is coupled to the native code generator and the dynamic code rewriter. The parser receives and parses a first dynamic code to divide the first dynamic code into compilable blocks and non-compilable blocks. The native code generator generates a native code according to the compilable blocks. The dynamic code rewriter rewrites the non-compilable blocks to generate a second dynamic code, wherein the second dynamic code has function calls which communicate between the native code and the first dynamic code.

Abstract: An exemplary embodiment of the present disclosure illustrates a hybrid dynamic code compiling device having a parser, a native code generator, and a dynamic code rewriter, wherein the parser is coupled to the native code generator and the dynamic code rewriter. The parser receives and parses a first dynamic code to divide the first dynamic code into compilable blocks and non-compilable blocks. The native code generator generates a native code according to the compilable blocks. The dynamic code rewriter rewrites the non-compilable blocks to generate a second dynamic code, wherein the second dynamic code has function calls which communicate between the native code and the first dynamic code.

Abstract: A system and method for configuring graphics register data and a recording medium are applied in a mobile device to store graphics operation data for displaying a picture. The system includes a plurality of register modules and an operation module. The operation module obtains unstored data from the graphics operation data, judges whether a register module already stored with data and having a configuration space sufficient for configuring the unstored data exists among all the plurality of register modules, so as to determine whether to store the unstored data into the register module already stored with data or a register module without storing-data, and when no register module without storing data exists and the configuration space of each register module already stored with data is insufficient for storing the unstored data, divides and stores the unstored data into a part of the plurality of register modules already stored with data.

Abstract: A system and method for configuring graphics register data and a recording medium are applied in a mobile device to store graphics operation data for displaying a picture. The system includes a plurality of register modules and an operation module. The operation module obtains unstored data from the graphics operation data, judges whether a register module already configured with data and having a configuration space sufficient for configuring the unstored data exists among all the register modules, so as to determine whether to store the unstored data into the register module already configured with data or a register module not configured with data, and when no register module not configured with data exists and the configuration space of each register module already configured with data is insufficient for storing the unstored data, divides and stores the unstored data into a part of the register modules already configured with data.

Abstract: A low power program compiling method includes the following steps: a program to be compiled is received. Wherein, the program includes several instructions to be compiled, the program is executed by an electrical device, which includes several candidate hardware units, after compiled. One of the candidate hardware units is selected as a target hardware unit. Several target hardware instructions, which access the target hardware unit, are detected from the instructions. The target hardware instructions are gathered into a hardware instruction block of the program. An enabling instruction for enabling the target hardware unit and a disabling instruction for disabling the target hardware are inserted before and after the hardware instruction block of the program respectively. The program is compiled after inserted to generate a compiled program.

Abstract: The invention relates to a multi-thread power gating control design, setting idle components into a sleep mode to reduce power consumption due to current leakage. Based on compiler techniques, the invention arranges predicted-power-gating instructions into every thread of a may-happen-in-parallel region. A predicted-power-on instruction determines whether the corresponding component has been powered on, and powers on the component when it has not been powered on yet. A predicted-power-off instruction determines whether the component is required in the rest of the may-happen-in-parallel region, and powers off the component when it is required later.

Abstract: A system chip includes a plurality of processing elements for performing primary computations of a plurality of tasks, a plurality of non-processing elements for controlling flow of data associated with the tasks among the processing elements, and a main controller including a scheduler, a resource allocation module, and a power management module. The scheduler assigns the tasks on the processing and non-processing elements with reference to time parameters of the processing and non-processing elements. The resource allocation module controls operations of the processing and non-processing elements with reference to task assignments determined by the scheduler. The power management module performs dynamic voltage management upon the processing and non-processing elements according to the scheduled tasks.

Abstract: A method of power-gating instruction scheduling for leakage power reduction comprises receiving a program, generating a control-flow graph dividing the program into a plurality of blocks, analyzing utilization of power-gated components of a processor executing the program, generating the first power-gating instruction placement comprising power-off instructions and power-on instructions to shut down the inactive power-gated components, generating the second power-gating instruction placement by merging the power-off instructions as one compound power-off instruction and merging the power-on instructions as one compound power-on instruction, and inserting power-gating instructions into the program in accordance with the second power-gating instruction placement.

Abstract: The invention relates to a multi-thread power gating control design, setting idle components into a sleep mode to reduce power consumption due to current leakage. Based on compiler techniques, the invention arranges predicted-power-gating instructions into every thread of a may-happen-in-parallel region. A predicted-power-on instruction determines whether the corresponding component has been powered on, and powers on the component when it has not been powered on yet. A predicted-power-off instruction determines whether the component is required in the rest of the may-happen-in-parallel region, and powers off the component when it is required later.

Abstract: A method of power-gating instruction scheduling for leakage power reduction comprises receiving a program, generating a control-flow graph dividing the program into a plurality of blocks, analyzing utilization of power-gated components of a processor executing the program, generating the first power-gating instruction placement comprising power-off instructions and power-on instructions to shut down the inactive power-gated components, generating the second power-gating instruction placement by merging the power-off instructions as one compound power-off instruction and merging the power-on instructions as one compound power-on instruction, and inserting power-gating instructions into the program in accordance with the second power-gating instruction placement.

Abstract: A system chip includes a plurality of processing elements for performing primary computations of a plurality of tasks, a plurality of non-processing elements for controlling flow of data associated with the tasks among the processing elements, and a main controller including a scheduler, a resource allocation module, and a power management module. The scheduler assigns the tasks on the processing and non-processing elements with reference to time parameters of the processing and non-processing elements. The resource allocation module controls operations of the processing and non-processing elements with reference to task assignments determined by the scheduler. The power management module performs dynamic voltage management upon the processing and non-processing elements according to the scheduled tasks.