Patents by Inventor Yi-Ping Yu

Yi-Ping Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Processor employing a power managing mechanism and method of saving power for the same
    Patent number: 7398410
    Abstract: A processor includes a plurality of execution units configured to execute instructions, a pre-decoder configured to sieve out a power-switching instruction from the instructions, and a power controller configured to control the status of the execution unit based on the power-switching instruction. The power controller includes an identification decoder configured to generate identifications respectively corresponding to the execution units from the power-switching instruction, and a power manager configured to switch the execution unit corresponding to the identification. Particularly, the power-switching instruction includes a power-on instruction and a power-off instruction. The processor further includes a plurality of reservation tables each configured to store the instruction to be executed by one of the execution units, and a turn-off signal is not conveyed to the power manager until the reservation table corresponding to the execution unit to be turned off is empty.
    Type: Grant
    Filed: July 8, 2005
    Date of Patent: July 8, 2008
    Assignee: National Tsing Hua University
    Inventors: Jenq-Kuen Lee, Yung-Chia Lin, Yi-Ping Yu, Chung-Wen Huang
  • Processor employing a power managing mechanism and method of saving power for the same
    Publication number: 20070011474
    Abstract: A processor includes a plurality of execution units configured to execute instructions, a pre-decoder configured to sieve out a power-switching instruction from the instructions, and a power controller configured to control the status of the execution unit based on the power-switching instruction. The power controller includes an identification decoder configured to generate identifications respectively corresponding to the execution units from the power-switching instruction, and a power manager configured to switch the execution unit corresponding to the identification. Particularly, the power-switching instruction includes a power-on instruction and a power-off instruction. The processor further includes a plurality of reservation tables each configured to store the instruction to be executed by one of the execution units, and a turn-off signal is not conveyed to the power manager until the reservation table corresponding to the execution unit to be turned off is empty.
    Type: Application
    Filed: July 8, 2005
    Publication date: January 11, 2007
    Applicant: NATIONAL TSING HUA UNIVERSITY
    Inventors: Jenq-Kuen Lee, Yung-Chia Lin, Yi-Ping Yu, Chung-Wen Huang