Abstract: Examples systems and methods for improved artificial intelligence generative model image attribution include a processor accessing instructions stored on a machine-readable storage medium. The instructions can be executable by the processor to obtain latent semantic dimensions by applying a principal component analysis on a latent distribution. Perturbations can be applied along the latent semantic dimensions according to a user-specific key and a predetermined perturbations strength to embed a model-specific fingerprint to embed a fingerprinted latent variable directly into the generative model such that the generative model generates images with model-specific fingerprints.

Abstract: Certain aspects of the present disclosure provide techniques for expediting mobility. One example method generally involves receiving signaling, from a serving cell of a first radio access technology (RAT), indicating a first list of frequencies associated with the first RAT and corresponding priority levels: performing idle measurements for frequencies in the first list, while camped on a serving cell of a second RAT: setting cell reselection thresholds to apply to the idle measurements for the frequencies in the first list, based on a relative priority of the serving cell of the second RAT to the frequencies in the first list: and performing cell reselection procedures based on the idle measurements for the frequencies and the determined cell reselection thresholds.

Abstract: A layer stack is formed over a conductive material portion located on a substrate. The layer stack contains a first silicon oxide layer, a silicon nitride layer formed by chemical vapor deposition, and a second silicon oxide layer. A patterned etch mask layer including an opening is formed over the layer stack. A via cavity extending through the layer stack and down to the conductive material portion is formed by isotropically etching portions of the layer stack underlying the opening in the patterned etch mask layer using an isotropic etch process. A buffered oxide etch process may be used, in which the etch rate of the silicon nitride layer is less than, but is significant enough, compared to the etch rate of the first silicon oxide layer to provide tapered straight sidewalls on the silicon nitride layer. An optical device including a patterned layer stack can be provided.

Abstract: Embodiments of the disclosure provide a solution for speech generation. A method includes: determining, based on a target text, a plurality of phoneme feature representations corresponding to a sequence of phonemes in the target text and respective phoneme durations for the plurality of phoneme feature representations; extending the plurality of phoneme feature representations based on the respective phoneme durations, to obtain an extended sequence of phoneme feature representations; masking at least one phoneme feature representation in the extended sequence of phoneme feature representations, to obtain a sequence of masked phoneme feature representations; and generating a target speech corresponding to the target text at least based on the sequence of masked phoneme feature representations.

Abstract: The present invention provides a general salt-assisted chemical vapor deposition (SA-CVD) synthetic method for the high-yield preparation of 1D hexagonal-phase MxV6S8(M=K, Rb, Cs) and KxV6SySe8-y nanowires. The resulting nanowires exhibit typical metallic properties, which can be used as a good van der Waals contact for achieving high-performance fermi level pinning free transistors. The present synthesis method allows a more systematic investigation of the intrinsic properties of hexagonal-phase V6S8 structures.

Abstract: Embodiments of the disclosure provide a solution for model training. A method includes: obtaining a training sample for training a machine learning model, the training sample comprising a sample speech, a sample text corresponding to the sample speech and speech duration information for the sample text, the machine learning model being configured to perform a plurality of tasks for speech processing; extracting a speech feature representation from the sample speech, a text feature representation from the sample text, a phoneme feature representation and a duration feature representation for the phoneme feature representation from the speech duration information; and training, according to the plurality of tasks, the machine learning model based on at least one of: the speech feature representation, the text feature representation or a combination of the phoneme feature representation and the duration feature representation.

Abstract: Semiconductor structures and methods for manufacturing the same are provided. The method includes nanostructures formed over a substrate, and a gate structure formed on the nanostructures. The semiconductor structure includes a source/drain (S/D) structure formed adjacent to the gate structure. The semiconductor structure includes a contact structure formed on the S/D structure, and a portion of the contact structure is embedded in the S/D structure, and the contact structure has a T-shaped structure.

Abstract: Methods, systems, and devices for wireless communications are described. Generally, a UE in a connected state with a cell of a first radio access technology (RAT) type may trigger a UE initiated inter-RAT redirection procedure to a neighboring cell of a different, higher priority level, RAT type if the network does not configure the UE to perform connected measurements for candidate neighbor cells of the higher priority level RAT type. A UE may receive an indication of candidate neighbor cells of a higher priority level RAT type. The UE may perform UE initiated measurements on the indicated candidate neighbor cells of the higher priority level RAT type. The UE may trigger an inter-RAT redirection procedure to one of the neighbor cells of the higher priority level RAT if the UE finds a suitable cell based on the UE initiated measurements.

Abstract: A flexible circuit board designed for chip integration is provided. The flexible circuit board includes an insulating substrate, a conductive copper layer, a first tin layer, a second tin layer, and a first solder resist layer. The first tin layer has a first tin thickness, and the second tin layer has a greater second tin thickness. A first tin surface of the first tin layer and a second tin surface of the second tin layer are substantially level.

Abstract: A semiconductor device structure and a method for forming a semiconductor device structure are provided. The method includes forming a metal gate stack wrapped around multiple semiconductor nanostructures, and the semiconductor nanostructures are adjacent to an epitaxial structure. The method also includes forming a dielectric layer over the metal gate stack and the epitaxial structure and partially removing the dielectric layer to form a contact opening exposing the epitaxial structure. The method further includes forming a first protective layer over sidewalls of the contact opening and forming a second protective layer over the first protective layer. The first protective layer has a lower dielectric constant than that of the second protective layer. In addition, the method includes forming a conductive contact over the second protective layer and the epitaxial structure to fill the contact opening.

Abstract: Embodiments of the present disclosure provide a task processing method and apparatus, an electronic device, and a storage medium. The method includes: sending first notification information to a client of at least one task to be delivered that is associated with a current preset location, where the first notification information includes a wait time; receiving first feedback information from the at least one client, and determining a suspended task for deferred processing based on the first feedback information; and in response to receiving a task processing request sent by a target client corresponding to a target suspended task, determining a target processing manner corresponding to the target suspended task based on a current location, to process the target suspended task based on the target processing manner.

Abstract: A method for forming a semiconductor structure is provided. The method includes forming a source/drain feature over an active region, forming a gate stack across the active region, forming an interlayer dielectric layer over the source/drain feature, and etching the interlayer dielectric layer to form an opening exposing the source/drain feature. The opening has a first sidewall extending in a first horizontal direction and a second sidewall extending in a second horizontal direction. The method also includes forming a contact liner along the opening, and forming a contact plug in the opening. A first portion of the contact liner along the first sidewall of the opening is thinner than a second portion of the contact liner along the second sidewall of the opening.

Abstract: A rotary engine that generates electricity using differences in relative humidity. A water-responsive material expands and contracts as water evaporates which drives the rotation of two wheels. The rotary motion drives an electrical generator which produces electricity. In another embodiment, the water-responsive material is used to actuate an artificial muscle of a robotic device.

Abstract: Embodiments of the present disclosure provide a robot dispatching method and apparatus, an electronic device, and a storage medium. The method includes: displaying at least one dispatchable robot available for switching in response to a robot switching instruction; and determining a target robot in response to a trigger operation for the at least one dispatchable robot, and sending robot information of the target robot to a dispatching system, so that the dispatching system associates a pending task associated with an abnormal robot with the target robot. According to the technical solutions of the embodiments of the present disclosure, an effect of switching to another robot to resume an associated task based on one-click operation is achieved, which in turn improves the universality and efficiency of a robot switching operation.

Abstract: Embodiments of the present disclosure provide a method and apparatus, an electronic device, and a storage medium for task processing. The method is applied to a robot and includes: displaying at least one display control and an abnormality reporting control on a display screen of the robot, where the display control is configured to display task-associated information of a task to be processed; displaying an abnormal task selection page in response to a trigger operation for the abnormality reporting control, to determine a target abnormal task based on a trigger operation on the abnormal task selection page, where the abnormal task selection page includes the at least one display control; and sending task-associated information and abnormality information of the target abnormal task to a target terminal in response to a trigger operation of uploading the target abnormal task.

Abstract: A semiconductor device includes a fin-shaped structure on the substrate, a shallow trench isolation (STI) around the fin-shaped structure, a single diffusion break (SDB) structure in the fin-shaped structure for dividing the fin-shaped structure into a first portion and a second portion; a first gate structure on the fin-shaped structure, a second gate structure on the STI, and a third gate structure on the SDB structure. Preferably, a width of the third gate structure is greater than a width of the second gate structure and each of the first gate structure, the second gate structure, and the third gate structure includes a U-shaped high-k dielectric layer, a U-shaped work function metal layer, and a low-resistance metal layer.

Abstract: Methods and apparatuses for recognizing a two-dimensional code are disclosed. In an implementation, a method comprises: identifying, by an electronic device, a two-dimensional code, wherein the two-dimensional code comprises an image region in the center and a ring region surrounding the image region, wherein the ring region comprises a code region including a first code region and a second code region, a first spacing region, and a second spacing region, wherein the first spacing region and the second spacing region are arranged between the first code region and the second code region, determining values corresponding to a plurality of code elements in the code region, and recognizing, by the electronic device based on the values, first information corresponding to the two-dimensional code.

Abstract: A semiconductor device includes a substrate, a plurality of oxide definition structures, a plurality of metal gates and a first conductive via. The oxide definition structures are formed on the substrate and arranged in a first direction. The metal gates are formed on the substrate and extend in a second direction. The first conductive via is formed on the substrate, located between two of the metal gates, extends in the first direction and has a first width in the second direction. There is a pitch between adjacent two of the metal gates in the second direction, and a first ratio of the first width to the pitch ranges between 0.2 and 0.7.

Abstract: Provided are dynamic sealing structure and rotary kiln apparatus. Dynamic sealing structure includes kiln tail, discharging cover, sealing mechanism, guiding mechanism and balancing device. Discharging cover includes discharging cover cylinder and discharging cover end face connected to same, discharging cover cylinder is arranged on outer side of circumferential wall of kiln tail in sleeving manner, and discharging cover end face and end face of the kiln tail are arranged at intervals. Sealing mechanism is arranged between discharging cover cylinder and kiln tail and is connected to inner wall of discharging cover cylinder. Guiding mechanism is arranged between inner wall of discharging cover cylinder and outer side of kiln tail, and is located on one side or two sides of sealing mechanism in axial direction of rotary kiln, rotating gap is provided between guiding mechanism and kiln tail, and balancing device is connected to outer side of the discharging cover cylinder.

Abstract: In some embodiments, the present disclosure relates to a piezomicroelectromechanical system (piezoMEMS) device that includes a second piezoelectric layer arranged over the first electrode layer. A second electrode layer is arranged over the second piezoelectric layer. A first contact is arranged over and extends through the second electrode layer and the second piezoelectric layer to contact the first electrode layer. A dielectric liner layer is arranged directly between the first contact and inner sidewalls of the second electrode layer and the second piezoelectric layer. A second contact is arranged over and electrically coupled to the second electrode layer, wherein the second contact is electrically isolated from the first contact.