Abstract: A test base cleaning line and a method thereof are provided. The test base cleaning line includes a plurality of cleaning mechanisms, a scanning device, and a moving device. The scanning device is configured for scanning a barcode on a test base to identify a type of the test base, and the moving device is configured for moving the test base to any one of the plurality of cleaning mechanisms according to the type of the test base so that the cleaning mechanism can perform a cleaning operation to the test base.

Abstract: A semiconductor device includes a substrate, a plurality of oxide definition structures, a plurality of metal gates and a first conductive via. The oxide definition structures are formed on the substrate and arranged in a first direction. The metal gates are formed on the substrate and extend in a second direction. The first conductive via is formed on the substrate, located between two of the metal gates, extends in the first direction and has a first width in the second direction. There is a pitch between adjacent two of the metal gates in the second direction, and a first ratio of the first width to the pitch ranges between 0.2 and 0.7.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a first side and a second side opposing the first side, a source/drain epitaxial feature disposed adjacent the first side of the substrate, wherein the source/drain epitaxial feature comprises a first epitaxial layer, a second epitaxial layer in contact with the first epitaxial layer, and a third epitaxial layer having sidewalls surrounded by and in contact with the second epitaxial layer. The device structure also includes a first silicide layer in contact with the substrate, the first, second, and third epitaxial layers, a first source/drain contact extending through the substrate from the first side to the second side, and a first metal capping layer disposed between the first silicide layer and the first source/drain contact.

Abstract: A test base cleaning line and a method thereof are provided. The test base cleaning line includes a plurality of cleaning mechanisms, a scanning device, and a moving device. The scanning device is configured for scanning a barcode on a test base to identify a type of the test base, and the moving device is configured for moving the test base to any one of the plurality of cleaning mechanisms according to the type of the test base so that the cleaning mechanism can perform a cleaning operation to the test base.

Abstract: A probe implanting equipment including: a base; a test socket disposed on the base and having a plurality of positioning holes; a mouthpiece configuration configured for providing a plurality of probes to the plurality of positioning holes; and a vibration device disposed on the base for effectively positioning the probes in the positioning holes of the test socket via vibration.

Abstract: A semiconductor device includes a substrate, a stack of semiconductor nanosheets, dielectric walls, a gate structure, and a vertical gate contact. The substrate includes nanosheet mesas, and the stack of semiconductor nanosheets is disposed on each of the nanosheet mesas. The dielectric walls cross through the nanosheet mesas and the stack of semiconductor nanosheets, wherein a top of each of the dielectric walls has a recess. The gate structure wraps the stack of semiconductor nanosheets and crosses over the dielectric walls. The vertical gate contact is disposed over the recess.

Abstract: A semiconductor device includes a substrate, parallel channel members, a gate structure, a source and drain feature, a source and drain contact, a top spacer portion, and a lining structure. The parallel channel members are spaced apart and stacked in parallel to the substrate. The parallel channel members include an uppermost channel member farthest from the substrate. The gate structure is wrapping around the channel members. The source and drain feature is disposed besides the channel members and the gate structure. The source and drain contact is disposed on the source and drain feature and besides the gate structure. The top spacer portion is disposed beside the gate structure, disposed on and in contact with the uppermost channel member. The lining structure is interposed between the source and drain contact and the top spacer portion. A bottom of the lining structure is located above the uppermost channel member.

Abstract: A semiconductor device includes an n-type transistor, a first contact segment, a p-type transistor and a second contact segment. Each of the n-type transistor and the p-type transistor includes a first source/drain region and a second source/drain region. The first contact segment partially overlaps the first source/drain region of the n-type transistor, and is in contact with the first source/drain region of the n-type transistor. The second contact segment partially overlaps the first source/drain region of the p-type transistor, and is in contact with the first source/drain region of the p-type transistor. A width of a portion of the first contact segment that overlaps the first source/drain region of the n-type transistor is different from a width of a portion of the second contact segment that overlaps the first source/drain region of the p-type transistor.

Abstract: An integrated circuit and a semiconductor chip are provided. The integrated circuit includes: an active region, defined on a substrate by a surrounding isolation structure; a gate structure, intersecting and covering the active region; a first source/drain contact pattern, intersecting the active region at a first side of the gate structure; and a second source/drain contact pattern, intersecting the active region at a second side of the gate structure, and having a first section crossing the active region and a second section extending away from the first section and overlapped with a power rail. The first section has a first width shorter than a second width of the second section.

Abstract: A semiconductor device includes a substrate, a stack of semiconductor nanosheets, a dielectric wall, and a gate structure. The substrate includes a nanosheet mesa, and the stack of semiconductor nanosheets is disposed on the nanosheet mesa. The dielectric wall crosses through the nanosheet mesa and the stack of semiconductor nanosheets. The gate structure wraps the stack of semiconductor nanosheets and crosses over the dielectric wall, wherein a top of the dielectric wall has a recess.

Abstract: Semiconductor structures and methods for manufacturing the same are provided. The method includes nanostructures formed over a substrate, and a gate structure formed on the nanostructures. The semiconductor structure includes a source/drain (S/D) structure formed adjacent to the gate structure. The semiconductor structure includes a contact structure formed on the S/D structure, and a portion of the contact structure is embedded in the S/D structure, and the contact structure has a T-shaped structure.

Abstract: A semiconductor device structure and a method for forming a semiconductor device structure are provided. The method includes forming a metal gate stack wrapped around multiple semiconductor nanostructures, and the semiconductor nanostructures are adjacent to an epitaxial structure. The method also includes forming a dielectric layer over the metal gate stack and the epitaxial structure and partially removing the dielectric layer to form a contact opening exposing the epitaxial structure. The method further includes forming a first protective layer over sidewalls of the contact opening and forming a second protective layer over the first protective layer. The first protective layer has a lower dielectric constant than that of the second protective layer. In addition, the method includes forming a conductive contact over the second protective layer and the epitaxial structure to fill the contact opening.

Abstract: A method for forming a semiconductor structure is provided. The method includes forming a source/drain feature over an active region, forming a gate stack across the active region, forming an interlayer dielectric layer over the source/drain feature, and etching the interlayer dielectric layer to form an opening exposing the source/drain feature. The opening has a first sidewall extending in a first horizontal direction and a second sidewall extending in a second horizontal direction. The method also includes forming a contact liner along the opening, and forming a contact plug in the opening. A first portion of the contact liner along the first sidewall of the opening is thinner than a second portion of the contact liner along the second sidewall of the opening.

Abstract: A semiconductor device includes a fin-shaped structure on the substrate, a shallow trench isolation (STI) around the fin-shaped structure, a single diffusion break (SDB) structure in the fin-shaped structure for dividing the fin-shaped structure into a first portion and a second portion; a first gate structure on the fin-shaped structure, a second gate structure on the STI, and a third gate structure on the SDB structure. Preferably, a width of the third gate structure is greater than a width of the second gate structure and each of the first gate structure, the second gate structure, and the third gate structure includes a U-shaped high-k dielectric layer, a U-shaped work function metal layer, and a low-resistance metal layer.

Abstract: A semiconductor device includes a substrate, a plurality of oxide definition structures, a plurality of metal gates and a first conductive via. The oxide definition structures are formed on the substrate and arranged in a first direction. The metal gates are formed on the substrate and extend in a second direction. The first conductive via is formed on the substrate, located between two of the metal gates, extends in the first direction and has a first width in the second direction. There is a pitch between adjacent two of the metal gates in the second direction, and a first ratio of the first width to the pitch ranges between 0.2 and 0.7.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack over the substrate. The semiconductor device structure includes a spacer over a side of the gate stack. The semiconductor device structure includes a dielectric layer over the substrate. The dielectric layer has a first recess, the dielectric layer has an upper portion and a first lower portion, the upper portion is over the first recess, the first recess is between the first lower portion and the spacer, and the upper portion has a convex curved sidewall.

Abstract: A semiconductor structure includes a substrate, a channel structure, a gate structure, two gate spacers and an insulating feature. The gate structure is disposed on the channel structure, and includes an upper gate portion which is located at a level higher than that of an uppermost surface of the channel structure. The two gate spacers are respectively located at two opposite sides of the upper gate portion, and each of the gate spacers has an upward surface having a concave profile. The insulating feature is disposed over the upper gate portion and against the concave profiles of the gate spacers to have an inverted U-shaped profile. The insulating feature includes a cap portion which is disposed on an upper surface of the upper gate portion and extends beyond an edge of the upper surface of the upper gate portion. Methods for manufacturing the semiconductor structure are also disclosed.

Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first semiconductor mesa formed on the semiconductor substrate within the first region; a second semiconductor mesa formed on the semiconductor substrate within the second region; and a field effect transistor (FET) formed on the semiconductor substrate. The FET includes a first doped feature of a first conductivity type formed in a top portion of the first semiconductor mesa; a second doped feature of a second conductivity type formed in a bottom portion of the first semiconductor mesa, the second semiconductor mesa, and a portion of the semiconductor substrate between the first and second semiconductor mesas; a channel in a middle portion of the first semiconductor mesa and interposed between the source and drain; and a gate formed on sidewall of the first semiconductor mesa.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a first side and a second side opposing the first side, a source/drain epitaxial feature disposed adjacent the first side of the substrate, wherein the source/drain epitaxial feature comprises a first epitaxial layer, a second epitaxial layer in contact with the first epitaxial layer, and a third epitaxial layer having sidewalls surrounded by and in contact with the second epitaxial layer. The device structure also includes a first silicide layer in contact with the substrate, the first, second, and third epitaxial layers, a first source/drain contact extending through the substrate from the first side to the second side, and a first metal capping layer disposed between the first silicide layer and the first source/drain contact.

Abstract: A semiconductor device includes a substrate, a stack of semiconductor nanosheets, a dielectric wall, and a gate structure. The substrate includes a nanosheet mesa, and the stack of semiconductor nanosheets is disposed on the nanosheet mesa. The dielectric wall crosses through the nanosheet mesa and the stack of semiconductor nanosheets. The gate structure wraps the stack of semiconductor nanosheets and crosses over the dielectric wall, wherein a top of the dielectric wall has a recess.