Abstract: A semiconductor device includes a substrate, a stack of semiconductor nanosheets, a dielectric wall, and a gate structure. The substrate includes a nanosheet mesa, and the stack of semiconductor nanosheets is disposed on the nanosheet mesa. The dielectric wall crosses through the nanosheet mesa and the stack of semiconductor nanosheets. The gate structure wraps the stack of semiconductor nanosheets and crosses over the dielectric wall, wherein a top of the dielectric wall has a recess.

Abstract: An embodiment for automatically controlling peripheral devices based on online meeting participant information. The embodiment may detect participants of an online meeting and generate a participant information table. The embodiment may generate a participant group table including one or more preliminary participant groups based on the participant information. The embodiment may generate and send audio through peripheral devices associated with at least one participant in each of the one or more preliminary participant groups to identify the participants in physically shared meeting spaces. The embodiment may update the participant group table to include confirmed participant groups based on the identified participants in the physically shared meeting spaces. The embodiment may determine a presenter for each of the confirmed participant groups and update the participant information.

Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first semiconductor mesa formed on the semiconductor substrate within the first region; a second semiconductor mesa formed on the semiconductor substrate within the second region; and a field effect transistor (FET) formed on the semiconductor substrate. The FET includes a first doped feature of a first conductivity type formed in a top portion of the first semiconductor mesa; a second doped feature of a second conductivity type formed in a bottom portion of the first semiconductor mesa, the second semiconductor mesa, and a portion of the semiconductor substrate between the first and second semiconductor mesas; a channel in a middle portion of the first semiconductor mesa and interposed between the source and drain; and a gate formed on sidewall of the first semiconductor mesa.

Abstract: Systems, devices and methods are provided for implanting medical devices into patients. The systems, devices and methods are particularly useful for orthopedic implants, such as spinal implants that facilitate fusion of bone segments. A fixation assembly for an implant comprises a screw having a head and a shaft, and a washer having at least one outer surface with one or more frictional elements for engaging a surface of the implant. The shaft includes one or more projections that cooperate with the washer to prevent the washer from sliding back down the screw, while allowing for easy application of the washer to ensure optimal placement and desired contact with the screw head. The washer and/or the screw head may also include interlocking cams that create a wedge effect that inhibits the screw from backing out or loosening from a hole in bone or other tissue.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack over the substrate. The semiconductor device structure includes a spacer over a side of the gate stack. The semiconductor device structure includes a dielectric layer over the substrate. The dielectric layer has a first recess, the dielectric layer has an upper portion and a first lower portion, the upper portion is over the first recess, the first recess is between the first lower portion and the spacer, and the upper portion has a convex curved sidewall.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack over the substrate, wherein the gate stack has a first portion and a second portion under the first portion, and the first portion is wider than the second portion. The semiconductor device structure includes a first spacer and a second spacer over opposite sides of the gate stack. The first spacer has a first upper portion and a first lower portion, the second spacer has a second upper portion and a second lower portion. The first spacer has a first recess, the first upper portion is between the first recess and the gate stack, the first lower portion is under the first recess, and the first recess has a first inner wall facing away from the gate stack.

Abstract: A pixel array substrate including a substrate, data lines, gate lines, pixels, and transfer lines is provided. The data lines are disposed on the substrate and arranged in a first direction. The gate lines are disposed on the substrate and arranged in a second direction interlaced with the first direction. The pixels are disposed on the substrate, each of which includes an active device electrically connected to one of the data lines and one of the gate lines and a pixel electrode electrically connected to the active device. The transfer lines are arranged in the first direction and electrically connected to the gate lines, respectively. The pixels include first pixels. In a top view of the pixel array substrate, at least one of the pixel electrodes of the first pixels is partially overlapped with one of the transfer lines. A driving method of a pixel array substrate is also provided.

Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first semiconductor mesa formed on the semiconductor substrate within the first region; a second semiconductor mesa formed on the semiconductor substrate within the second region; and a field effect transistor (FET) formed on the semiconductor substrate. The FET includes a first doped feature of a first conductivity type formed in a top portion of the first semiconductor mesa; a second doped feature of a second conductivity type formed in a bottom portion of the first semiconductor mesa, the second semiconductor mesa, and a portion of the semiconductor substrate between the first and second semiconductor mesas; a channel in a middle portion of the first semiconductor mesa and interposed between the source and drain; and a gate formed on sidewall of the first semiconductor mesa.

Abstract: A pixel array substrate including a substrate, pixel structures, and transfer lines is provided. The pixel structures are disposed on the substrate. Each pixel structure includes a data line, a gate line, an active device, and a pixel electrode. The active device is electrically connected to the data line and the gate line. The pixel electrode is electrically connected to the active device. The pixel electrode defines alignment domains. The alignment domains have different alignment directions. The transfer lines are arranged in a first direction. Gate lines of the pixel structures are arranged in a second direction. The first direction and the second direction are interlaced. The transfer lines are electrically connected to the gate lines. The pixel structures include a first pixel structure. The transfer lines include a first transfer line. The first transfer line overlaps a boundary between the alignment domains of the first pixel structure.

Abstract: A pixel array substrate including a substrate, data lines, gate lines, pixels, and transfer lines is provided. The data lines are disposed on the substrate and arranged in a first direction. The gate lines are disposed on the substrate and arranged in a second direction interlaced with the first direction. The pixels are disposed on the substrate, each of which includes an active device electrically connected to one of the data lines and one of the gate lines and a pixel electrode electrically connected to the active device. The transfer lines are arranged in the first direction and electrically connected to the gate lines, respectively. The pixels include first pixels. In a top view of the pixel array substrate, at least one of the pixel electrodes of the first pixels is partially overlapped with one of the transfer lines. A driving method of a pixel array substrate is also provided.

Abstract: A pixel array substrate including a substrate, data lines, gate lines, pixels, and transfer lines is provided. The data lines are disposed on the substrate and arranged in a first direction. The gate lines are disposed on the substrate and arranged in a second direction interlaced with the first direction. The pixels are disposed on the substrate, each of which includes an active device electrically connected to one of the data lines and one of the gate lines and a pixel electrode electrically connected to the active device. The transfer lines are arranged in the first direction and electrically connected to the gate lines, respectively. The pixels include first pixels. In a top view of the pixel array substrate, at least one of the pixel electrodes of the first pixels is partially overlapped with one of the transfer lines. A driving method of a pixel array substrate is also provided.

Abstract: A pixel array substrate including a substrate, data lines, gate lines, pixels, and transfer lines is provided. The data lines are disposed on the substrate and arranged in a first direction. The gate lines are disposed on the substrate and arranged in a second direction interlaced with the first direction. The pixels are disposed on the substrate, each of which includes an active device electrically connected to one of the data lines and one of the gate lines and a pixel electrode electrically connected to the active device. The transfer lines are arranged in the first direction and electrically connected to the gate lines, respectively. The pixels include first pixels. In a top view of the pixel array substrate, at least one of the pixel electrodes of the first pixels is partially overlapped with one of the transfer lines. A driving method of a pixel array substrate is also provided.

Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first semiconductor mesa formed on the semiconductor substrate within the first region; a second semiconductor mesa formed on the semiconductor substrate within the second region; and a field effect transistor (FET) formed on the semiconductor substrate. The FET includes a first doped feature of a first conductivity type formed in a top portion of the first semiconductor mesa; a second doped feature of a second conductivity type formed in a bottom portion of the first semiconductor mesa, the second semiconductor mesa, and a portion of the semiconductor substrate between the first and second semiconductor mesas; a channel in a middle portion of the first semiconductor mesa and interposed between the source and drain; and a gate formed on sidewall of the first semiconductor mesa.

Abstract: A semiconductor device includes a fin-shaped structure on the substrate, a shallow trench isolation (STI) around the fin-shaped structure, a single diffusion break (SDB) structure in the fin-shaped structure for dividing the fin-shaped structure into a first portion and a second portion; a first gate structure on the fin-shaped structure, a second gate structure on the STI, and a third gate structure on the SDB structure. Preferably, a width of the third gate structure is greater than a width of the second gate structure and each of the first gate structure, the second gate structure, and the third gate structure includes a U-shaped high-k dielectric layer, a U-shaped work function metal layer, and a low-resistance metal layer.

Abstract: A semiconductor device includes: a fin-shaped structure on the substrate; a shallow trench isolation (STI) around the fin-shaped structure; a single diffusion break (SDB) structure in the fin-shaped structure for dividing the fin-shaped structure into a first portion and a second portion; a first gate structure on the fin-shaped structure; a second gate structure on the STI; and a third gate structure on the SDB structure, wherein a width of the third gate structure is greater than a width of the second gate structure.

Abstract: A pixel array substrate including a substrate, pixel structures, and transfer lines is provided. The pixel structures are disposed on the substrate. Each pixel structure includes a data line, a gate line, an active device, and a pixel electrode. The active device is electrically connected to the data line and the gate line. The pixel electrode is electrically connected to the active device. The pixel electrode defines alignment domains. The alignment domains have different alignment directions. The transfer lines are arranged in a first direction. Gate lines of the pixel structures are arranged in a second direction. The first direction and the second direction are interlaced. The transfer lines are electrically connected to the gate lines. The pixel structures include a first pixel structure. The transfer lines include a first transfer line. The first transfer line overlaps a boundary between the alignment domains of the first pixel structure.

Abstract: A pixel array substrate including a substrate, data lines, gate lines, pixels, and transfer lines is provided. The data lines are disposed on the substrate and arranged in a first direction. The gate lines are disposed on the substrate and arranged in a second direction interlaced with the first direction. The pixels are disposed on the substrate, each of which includes an active device electrically connected to one of the data lines and one of the gate lines and a pixel electrode electrically connected to the active device. The transfer lines are arranged in the first direction and electrically connected to the gate lines, respectively. The pixels include first pixels. In a top view of the pixel array substrate, at least one of the pixel electrodes of the first pixels is partially overlapped with one of the transfer lines. A driving method of a pixel array substrate is also provided.

Abstract: A pixel array substrate including a substrate, data lines, gate lines, pixels, and transfer lines is provided. The data lines are disposed on the substrate and arranged in a first direction. The gate lines are disposed on the substrate and arranged in a second direction interlaced with the first direction. The pixels are disposed on the substrate, each of which includes an active device electrically connected to one of the data lines and one of the gate lines and a pixel electrode electrically connected to the active device. The transfer lines are arranged in the first direction and electrically connected to the gate lines, respectively. The pixels include first pixels. In a top view of the pixel array substrate, at least one of the pixel electrodes of the first pixels is partially overlapped with one of the transfer lines. A driving method of a pixel array substrate is also provided.

Abstract: A pixel array substrate including a substrate, data lines, gate lines, pixels, and transfer lines is provided. The data lines are disposed on the substrate and arranged in a first direction. The gate lines are disposed on the substrate and arranged in a second direction interlaced with the first direction. The pixels are disposed on the substrate, each of which includes an active device electrically connected to one of the data lines and one of the gate lines and a pixel electrode electrically connected to the active device. The transfer lines are arranged in the first direction and electrically connected to the gate lines, respectively. The pixels include first pixels. In a top view of the pixel array substrate, at least one of the pixel electrodes of the first pixels is partially overlapped with one of the transfer lines. A driving method of a pixel array substrate is also provided.

Abstract: A pixel array substrate including a substrate, data lines, gate lines, pixels, and transfer lines is provided. The data lines are disposed on the substrate and arranged in a first direction. The gate lines are disposed on the substrate and arranged in a second direction interlaced with the first direction. The pixels are disposed on the substrate, each of which includes an active device electrically connected to one of the data lines and one of the gate lines and a pixel electrode electrically connected to the active device. The transfer lines are arranged in the first direction and electrically connected to the gate lines, respectively. The pixels include first pixels. In a top view of the pixel array substrate, at least one of the pixel electrodes of the first pixels is partially overlapped with one of the transfer lines. A driving method of a pixel array substrate is also provided.