Abstract: Output data lines generate data according to a corresponding sampling clock. For each output data line, a latch cascade is provided. Each latch cascade has an input end and an output end, and includes at least one latch. Data presented at the input end of a latch cascade cascades through the latch cascade and is presented at the output end of the latch cascade. The output end of each latch cascade is a final latch in the latch cascade. Each output data line is respectively connected to the input end of one of the latch cascades. The final latch in each latch cascade is triggered by a common clock signal. Finally, for each latch cascade having two or more latches, a triggering clock triggers an initial latch in each latch cascade. The triggering clock is phase shifted after the sampling clock of the corresponding output data line. This corresponding output data line is connected to the initial latch.

Abstract: An impedance matching circuit includes a plurality of latch circuits, each connected to one of a plurality of logic circuits. Each latch circuit has a first input commonly connected to a signal line and a second input connected to one of a plurality of non-overlapping digital clock signals. Approximately half of the maximum output resistance is compared with an external resistor and the result latched by a latch circuit corresponding to the most significant bit of the control signal, effectively halving the possible voltage range. A next latch circuit latches the second most significant bit of the control signal similarly, and a third latch circuit latches the remaining bit of the control signal. The control signal controls a binary weighted transistor array that adjusts input voltage. An output signal goes to an output register where it is used to control an output driver.

Abstract: A nozzle plate and a method of fabricating a nozzle plate on an inkjet print head are provided. A patterned first nozzle layer is formed over an ink wall layer over the inkjet print head. The first nozzle layer has at least a first opening. The wall of the first opening is treated to form a hydrophilic surface. Thereafter, a patterned second nozzle layer is formed over the first nozzle layer. The second nozzle layer has at least a second opening having connection with the first opening. The wall of the second opening is treated to form a hydrophobic surface. The first nozzle layer and the second nozzle layer together form a nozzle plate. The first opening and the second opening together form a nozzle with the lower section of the wall hydrophilic but the upper section of the wall hydrophobic.

Abstract: The small swing output buffer of the present invention comprises, for example, four transistors or FETs; P1, P2, N1, and N2. The source of P2 is connected to Vcc and the drain of P2 is connected to the source of P1. The drain of PI is connected to the source of N1. The drain of N1 is connected to the source of N2. The drain of N2 is connected to ground. The input signal to the output buffer is fed into input IN which is connected to the gates of P1 and N1. The output of the output buffer is output OUT which is connected to the drain of P1 and the source of N1. For the small swing output buffer, when the input signal is at a high potential, P1 and P2 are turned off and N1 and N2 are turned on which pulls down the potential of OUT towards ground potential. Since FETs have a threshold voltage, the potential of the output OUT cannot be completely pulled to ground potential. Therefore, the potential of the output OUT when the input signal applied to IN is a high potential, is the threshold voltage (Vt) of N2.

Abstract: The high-speed, low setup time, voltage-sensing flip-flop of an embodiment of the present invention comprises a master stage and a slave stage. The master stage has a data input and a clock input. The slave stage receives two signal lines from the master stage. When the clock input is low, the two input lines to the slave stage are pulled high. This turns on two transistors and precharges the inputs to the slave stage. When the clock makes a high transition, the pullup transistors in the master stage are turned off which decouples the inputs of the slave stage from the output of the master stage. At this time, if the data input is high, the A input to the slave stage is discharged. If the data input is low, the B input to the slave stage is discharged. After the two inputs to the slave stage are decoupled from the master stage, any change in the data input signal causes the inputs to the slave stage to float low since the two lines are not pulled high or low.

Abstract: A current-sensing static amplifier-based flip-flop is useful for high-performance VLSI circuitry. The flip-flop has a short latency and a small hold time, advantageous features in high-performance microprocessors. A flip-flop circuit includes an amplifier stage and a static stage. The amplifier stage has a data input terminal and a clock input terminal. The amplifier stage includes a dual-output amplifier having two output lines connected respectively to two current pulldown paths and a gate connected between the current pulldown paths. The static stage is connected to the amplifier stage and including a static latch.