Patents by Inventor Yi-Ren Warry Hwang

Yi-Ren Warry Hwang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Output buffer including an application-specific SRAM memory cell for low voltage, high speed operation
    Patent number: 6046942
    Abstract: An application-specific SRAM memory cell includes first and second cross-coupled inverters coupled at first and second nodes for storing a bit of information at the first node and a complement of the bit at the second node, first and second series-connected transistors for coupling a write data signal to the first node in response to a write address signal and a clock having high logical values, third, fourth and fifth series-connected transistors for coupling the second node to ground in response to the write data signal, the write address signal and the clock having high logical values, a sixth transistor for coupling the bit to a read data line in response to a read address signal having a high logical value, a seventh transistor for coupling the complement of the bit to a third node in response to the read address signal having a high logical value, an eighth transistor for coupling the read data line to a power supply terminal in response to the third node having a low logical value, and a ninth transist
    Type: Grant
    Filed: September 21, 1998
    Date of Patent: April 4, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Yi-Ren Warry Hwang, Luigi DiGregorio
  • Application-specific SRAM memory cell for low voltage, high speed operation
    Patent number: 5870331
    Abstract: An application-specific SRAM memory cell includes first and second cross-coupled inverters coupled at first and second nodes for storing a bit of information at the first node and a complement of the bit at the second node, first and second series-connected transistors for coupling a write data signal to the first node in response to a write address signal and a clock having high logical values, third, fourth and fifth series-connected transistors for coupling the second node to ground in response to the write data signal, the write address signal and the clock having high logical values, a sixth transistor for coupling the bit to a read data line in response to a read address signal having a high logical value, a seventh transistor for coupling the complement of the bit to a third node in response to the read address signal having a high logical value, an eighth transistor for coupling the read data line to a power supply terminal in response to the third node having a low logical value, and a ninth transist
    Type: Grant
    Filed: September 26, 1997
    Date of Patent: February 9, 1999
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Yi-Ren Warry Hwang, Luigi DiGregorio