Abstract: A depletion type vertical discrete NMOS device includes: an N-type epitaxial layer formed on an N-type substrate, wherein the N-type epitaxial layer has a top surface and a bottom surface opposite to each other; a P-type well formed in the N-type epitaxial layer; a gate formed outside and connected with the N-type epitaxial layer; an N-type source formed in the N-type epitaxial layer and in contact with the P-type well; an N-type drain including a part of the N-type substrate, which is formed outside and under the N-type epitaxial layer; and an N-type region formed and connected between the P-type well and the gate, which provides a channel, such that the N-type source and the N-type drain are electrically connected with each other during conduction operation, whereas, the N-type source and the N-type drain are electrically disconnected from each other during non-conduction operation.

Abstract: A high voltage device includes: a semiconductor layer, a well, a body region, a gate, a source, a drain, and a drift oxide region. The semiconductor layer is formed on a substrate, wherein the semiconductor layer has at least one trench. The well is formed in the semicoducotor layer. The body region is formed in the well. The gate is formed on the well, and is in contact with the well. The source and the drain are located below, outside, and at different sides of the gate, in the body region and the well respectively. The drift oxide region is formed on a drift region, wherein a bottom surface of the drift oxide region is higher than a bottom surface of the trench.

Abstract: A high voltage device includes: a semiconductor layer, a well, a body region, a gate, a source, a drain, and a drift oxide region. The semiconductor layer is formed on a substrate, wherein the semiconductor layer has at least one trench. The well is formed in the semiconductor layer. The body region is formed in the well. The gate is formed on the well, and is in contact with the well. The source and the drain are located below, outside, and at different sides of the gate, in the body region and the well respectively. The drift oxide region is formed on a drift region, wherein a bottom surface of the drift oxide region is higher than a bottom surface of the trench.

Abstract: A high-voltage semiconductor device has a main high-voltage switch device and a current-sense device for mirroring the current through the main high-voltage switch device. The main high-voltage switch device has a plurality of switch cells arranged to form a first array on a semiconductor substrate. Each switch cell has a first cell width. The current-sense device has a plurality of sense cells arranged to form a second array on the semiconductor substrate. Each sense cell has a second cell width larger than the first cell width. The switch cells and the sense cells share a common gate electrode and a common drain electrode.

Abstract: A power metal-oxide-semiconductor field-effect transistor (MOSFET) device includes a first metal layer, a substrate, an epitaxy layer, a plurality of first trench wells, a plurality of second trench wells, a plurality of body structure layers, a plurality of polysilicon layers, and a second metal layer. A part of a depletion region is formed between each first trench well and the epitaxy layer and between a body structure layer corresponding to the each first trench well and the epitaxy layer, and a rest part of the depletion region is formed between a second trench well corresponding to the each first trench well and the epitaxy layer. The plurality of second trench wells increase a breakdown voltage of the power MOSFET device and reduce a conduction resistor of the power MOSFET device.

Abstract: A high-voltage semiconductor device has a main high-voltage switch device and a current-sense device for mirroring the current through the main high-voltage switch device. The main high-voltage switch device has a plurality of switch cells arranged to form a first array on a semiconductor substrate. Each switch cell has a first cell width. The current-sense device has a plurality of sense cells arranged to form a second array on the semiconductor substrate. Each sense cell has a second cell width larger than the first cell width. The switch cells and the sense cells share a common gate electrode and a common drain electrode.

Abstract: A power metal-oxide-semiconductor field-effect transistor (MOSFET) device includes a first metal layer, a substrate, an epitaxy layer, a plurality of first trench wells, a plurality of second trench wells, a plurality of body structure layers, a plurality of polysilicon layers, and a second metal layer. A part of a depletion region is formed between each first trench well and the epitaxy layer and between a body structure layer corresponding to the each first trench well and the epitaxy layer, and a rest part of the depletion region is formed between a second trench well corresponding to the each first trench well and the epitaxy layer. The plurality of second trench wells increase a breakdown voltage of the power MOSFET device and reduce a conduction resistor of the power MOSFET device.