Patents by Inventor Yi-Ruei Lin

Yi-Ruei Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220273735
    Abstract: The invention provides a method of increasing an amount of oral immunoglobulin A (IgA) and/or inhibiting oral pathogens in a subject in need thereof, which utilizes a composition including a therapeutically effective amount of probiotics as an effective ingredient. The probiotics include Lactobacillus plantarum LPL28, which can efficiently increase the amount of oral IgA and/or inhibit the oral pathogens, and thus have a potential to prevent teeth cavities and/or periodontal diseases.
    Type: Application
    Filed: October 27, 2021
    Publication date: September 1, 2022
    Inventors: Hsieh-Hsun Ho, Wen-Yang Lin, Yi-Wei Kuo, Yen-Yu Huang, Jia-Hung Lin, Chi-Huei Lin, Cheng-Ruei Liu, Shu-Hui Chen
  • Publication number: 20220270934
    Abstract: A method of fabricating a device includes forming a dummy gate over a plurality of fins. Thereafter, a first portion of the dummy gate is removed to form a first trench that exposes a first hybrid fin and a first part of a second hybrid fin. The method further includes filling the first trench with a dielectric material disposed over the first hybrid fin and over the first part of the second hybrid fin. Thereafter, a second portion of the dummy gate is removed to form a second trench and the second trench is filled with a metal layer. The method further includes etching-back the metal layer, where a first plane defined by a first top surface of the metal layer is disposed beneath a second plane defined by a second top surface of a second part of the second hybrid fin after the etching-back the metal layer.
    Type: Application
    Filed: May 9, 2022
    Publication date: August 25, 2022
    Inventors: Kuan-Ting PAN, Huan-Chieh SU, Zhi-Chang LIN, Shi Ning JU, Yi-Ruei JHAN, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Patent number: 10204843
    Abstract: A semiconductor device structure and a method of fabricating the same are provided. The method for manufacturing a semiconductor structure includes forming a dielectric layer over a substrate and forming a first structure through the dielectric layer such that a first portion of the dielectric layer is disposed in between the first structure. The method for manufacturing a semiconductor structure further includes forming a first via hole and a second via hole through the first portion of the dielectric layer and forming a trench connecting the first via hole and the second via hole in the dielectric layer. The method for manufacturing a semiconductor structure further includes forming a conductive feature in the first via hole, the second via hole, and the trench. In addition, the first structure and the dielectric layer are made of different materials from each other.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: February 12, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Ruei Lin, Yen-Ming Peng, Han-Wei Yang, Chen-Chung Lai
  • Patent number: 10014251
    Abstract: A semiconductor device with the metal fuse is provided. The metal fuse connects an electronic component (e.g., a transistor) and a existing dummy feature which is grounded. The protection of the metal fuse can be designed to start at the beginning of the metallization formation processes. The grounded dummy feature provides a path for the plasma charging to the ground during the entire back end of the line process. The metal fuse is a process level protection as opposed to the diode, which is a circuit level protection. As a process level protection, the metal fuse protects subsequently-formed circuitry. In addition, no additional active area is required for the metal fuse in the chip other than internal dummy patterns that are already implemented.
    Type: Grant
    Filed: March 5, 2016
    Date of Patent: July 3, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Chung Lai, Kang-Min Kuo, Yen-Ming Peng, Gwo-Chyuan Kuoh, Han-Wei Yang, Yi-Ruei Lin, Chin-Chia Chang, Ying-Chieh Liao, Che-Chia Hsu, Bor-Zen Tien
  • Publication number: 20180076109
    Abstract: A semiconductor device structure and a method of fabricating the same are provided. The method for manufacturing a semiconductor structure includes forming a dielectric layer over a substrate and forming a first structure through the dielectric layer such that a first portion of the dielectric layer is disposed in between the first structure. The method for manufacturing a semiconductor structure further includes forming a first via hole and a second via hole through the first portion of the dielectric layer and forming a trench connecting the first via hole and the second via hole in the dielectric layer. The method for manufacturing a semiconductor structure further includes forming a conductive feature in the first via hole, the second via hole, and the trench. In addition, the first structure and the dielectric layer are made of different materials from each other.
    Type: Application
    Filed: November 9, 2017
    Publication date: March 15, 2018
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Ruei LIN, Yen-Ming PENG, Han-Wei YANG, Chen-Chung LAI
  • Patent number: 9818666
    Abstract: A semiconductor device structure and a method of fabricating the same are provided. The semiconductor device structure includes a gate structure embedded in a first dielectric layer over a substrate and a second dielectric layer formed over the first dielectric layer. The semiconductor device structure includes a conductive feature formed in the second dielectric layer over the gate structure and a first structure formed at least two sides of the conductive feature in the second dielectric layer. The first dielectric layer is made of a compressive material and the first structure is made of a tensile material or wherein the first dielectric layer is made of a compressive material and the first structure is made of a tensile material.
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: November 14, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Ruei Lin, Yen-Ming Peng, Han-Wei Yang, Chen-Chung Lai
  • Publication number: 20170033030
    Abstract: A semiconductor device structure and a method of fabricating the same are provided. The semiconductor device structure includes a gate structure embedded in a first dielectric layer over a substrate and a second dielectric layer formed over the first dielectric layer. The semiconductor device structure includes a conductive feature formed in the second dielectric layer over the gate structure and a first structure formed at least two sides of the conductive feature in the second dielectric layer. The first dielectric layer is made of a compressive material and the first structure is made of a tensile material or wherein the first dielectric layer is made of a compressive material and the first structure is made of a tensile material.
    Type: Application
    Filed: October 17, 2016
    Publication date: February 2, 2017
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Ruei LIN, Yen-Ming PENG, Han-Wei YANG, Chen-Chung LAI
  • Patent number: 9472508
    Abstract: A semiconductor device structure and a method of fabricating the same are provided. The semiconductor structure includes a substrate and an interconnection structure formed over the substrate. The interconnection structure includes a first dielectric layer and a first stress-reducing structure formed in the first dielectric layer. The interconnection structure further includes a first conductive feature formed in the first dielectric layer, and the first conductive feature is surrounded by the first stress-reducing structure.
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: October 18, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Ruei Lin, Yen-Ming Peng, Han-Wei Yang, Chen-Chung Lai
  • Publication number: 20160190064
    Abstract: A semiconductor device with the metal fuse is provided. The metal fuse connects an electronic component (e.g., a transistor) and a existing dummy feature which is grounded. The protection of the metal fuse can be designed to start at the beginning of the metallization formation processes. The grounded dummy feature provides a path for the plasma charging to the ground during the entire back end of the line process. The metal fuse is a process level protection as opposed to the diode, which is a circuit level protection. As a process level protection, the metal fuse protects subsequently-formed circuitry. In addition, no additional active area is required for the metal fuse in the chip other than internal dummy patterns that are already implemented.
    Type: Application
    Filed: March 5, 2016
    Publication date: June 30, 2016
    Inventors: Chen-Chung LAI, Kang-Min KUO, Yen-Ming PENG, Gwo-Chyuan KUOH, Han-Wei YANG, Yi-Ruei LIN, Chin-Chia CHANG, Ying-Chieh LIAO, Che-Chia HSU, Bor-Zen TIEN
  • Publication number: 20160118350
    Abstract: A semiconductor device structure and a method of fabricating the same are provided. The semiconductor structure includes a substrate and an interconnection structure formed over the substrate. The interconnection structure includes a first dielectric layer and a first stress-reducing structure formed in the first dielectric layer. The interconnection structure further includes a first conductive feature formed in the first dielectric layer, and the first conductive feature is surrounded by the first stress-reducing structure.
    Type: Application
    Filed: January 4, 2016
    Publication date: April 28, 2016
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Ruei LIN, Yen-Ming PENG, Han-Wei YANG, Chen-Chung LAI
  • Patent number: 9299621
    Abstract: An integrated circuit includes a number of lateral diffusion measurement structures arranged on a silicon substrate. A lateral diffusion measurement structure includes a p-type region and an n-type region which cooperatively span a predetermined initial distance between opposing outer edges of the lateral diffusion measurement structure. The p-type and n-type regions meet at a p-n junction expected to be positioned at a target junction location after dopant diffusion has occurred.
    Type: Grant
    Filed: September 12, 2013
    Date of Patent: March 29, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Han-Wei Yang, Yi-Ruei Lin, Chen-Chung Lai, Kang-Min Kuo, Bor-Zen Tien
  • Patent number: 9299658
    Abstract: A semiconductor device with the metal fuse and a fabricating method thereof are provided. The metal fuse connects an electronic component (e.g., a transistor) and a existing dummy feature which is grounded. The protection of the metal fuse can be designed to start at the beginning of the metallization formation processes. The grounded dummy feature provides a path for the plasma charging to the ground during the entire back end of the line process. The metal fuse is a process level protection as opposed to the diode, which is a circuit level protection. As a process level protection, the metal fuse protects subsequently-formed circuitry. In addition, no additional active area is required for the metal fuse in the chip other than internal dummy patterns that are already implemented.
    Type: Grant
    Filed: May 20, 2015
    Date of Patent: March 29, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Chung Lai, Kang-Min Kuo, Yen-Ming Peng, Gwo-Chyuan Kuoh, Han-Wei Yang, Yi-Ruei Lin, Chin-Chia Chang, Ying-Chieh Liao, Che-Chia Hsu, Bor-Zen Tien
  • Patent number: 9252047
    Abstract: Embodiments of a semiconductor device structure and a method of fabricating the same are provided. The semiconductor device structure includes a substrate and a first layer formed over the substrate. The semiconductor device structure further includes a stress-reducing structure formed in the first layer, and a portion of the first layer is surrounded by the stress-reducing structure. The semiconductor device structure further includes a conductive feature formed in the portion of the first layer surrounded by the stress-reducing structure.
    Type: Grant
    Filed: January 23, 2014
    Date of Patent: February 2, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Yi-Ruei Lin, Yen-Ming Peng, Han-Wei Yang, Chen-Chung Lai
  • Publication number: 20150255394
    Abstract: A semiconductor device with the metal fuse and a fabricating method thereof are provided. The metal fuse connects an electronic component (e.g., a transistor) and a existing dummy feature which is grounded. The protection of the metal fuse can be designed to start at the beginning of the metallization formation processes. The grounded dummy feature provides a path for the plasma charging to the ground during the entire back end of the line process. The metal fuse is a process level protection as opposed to the diode, which is a circuit level protection. As a process level protection, the metal fuse protects subsequently-formed circuitry. In addition, no additional active area is required for the metal fuse in the chip other than internal dummy patterns that are already implemented.
    Type: Application
    Filed: May 20, 2015
    Publication date: September 10, 2015
    Inventors: Chen-Chung LAI, Kang-Min KUO, Yen-Ming PENG, Gwo-Chyuan KUOH, Han-Wei YANG, Yi-Ruei LIN, Chin-Chia CHANG, Ying-Chieh LIAO, Che-Chia HSU, Bor-Zen TIEN
  • Publication number: 20150206845
    Abstract: Embodiments of a semiconductor device structure and a method of fabricating the same are provided. The semiconductor device structure includes a substrate and a first layer formed over the substrate. The semiconductor device structure further includes a stress-reducing structure formed in the first layer, and a portion of the first layer is surrounded by the stress-reducing structure. The semiconductor device structure further includes a conductive feature formed in the portion of the first layer surrounded by the stress-reducing structure.
    Type: Application
    Filed: January 23, 2014
    Publication date: July 23, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Yi-Ruei LIN, Yen-Ming PENG, Han-Wei YANG, Chen-Chung LAI
  • Patent number: 9070687
    Abstract: A semiconductor device with the metal fuse is provided. The metal fuse connects an electronic component (e.g., a transistor) and a existing dummy feature which is grounded. The protection of the metal fuse can be designed to start at the beginning of the metallization formation processes. The grounded dummy feature provides a path for the plasma charging to the ground during the entire back end of the line process. The metal fuse is a process level protection as opposed to the diode, which is a circuit level protection. As a process level protection, the metal fuse protects subsequently-formed circuitry. In addition, no additional active area is required for the metal fuse in the chip other than internal dummy patterns that are already implemented.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: June 30, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Chung Lai, Kang-Min Kuo, Yen-Ming Peng, Gwo-Chyuan Kuoh, Han-Wei Yang, Yi-Ruei Lin, Chin-Chia Chang, Ying-Chieh Liao, Che-Chia Hsu, Bor-Zen Tien
  • Publication number: 20150069395
    Abstract: An integrated circuit includes a number of lateral diffusion measurement structures arranged on a silicon substrate. A lateral diffusion measurement structure includes a p-type region and an n-type region which cooperatively span a predetermined initial distance between opposing outer edges of the lateral diffusion measurement structure. The p-type and n-type regions meet at a p-n junction expected to be positioned at a target junction location after dopant diffusion has occurred.
    Type: Application
    Filed: September 12, 2013
    Publication date: March 12, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Han-Wei Yang, Yi-Ruei Lin, Chen-Chung Lai, Kang-Min Kuo, Bor-Zen Tien
  • Publication number: 20150001592
    Abstract: A semiconductor device with the metal fuse is provided. The metal fuse connects an electronic component (e.g., a transistor) and a existing dummy feature which is grounded. The protection of the metal fuse can be designed to start at the beginning of the metallization formation processes. The grounded dummy feature provides a path for the plasma charging to the ground during the entire back end of the line process. The metal fuse is a process level protection as opposed to the diode, which is a circuit level protection. As a process level protection, the metal fuse protects subsequently-formed circuitry. In addition, no additional active area is required for the metal fuse in the chip other than internal dummy patterns that are already implemented.
    Type: Application
    Filed: June 28, 2013
    Publication date: January 1, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., LTD.
    Inventors: Chen-Chung Lai, Kang-Min Kuo, Yen-Ming Peng, Gwo-Chyuan Kuoh, Han-Wei Yang, Yi-Ruei Lin, Chin-Chia Chang, Ying-Chieh Liao, Che-Chia Hsu, Bor-Zen Tien