Patents by Inventor Yi-Rui Chen

Yi-Rui Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250226359
    Abstract: A method for manufacturing a semiconductor structure includes: forming a first bonding layer on a device substrate, the first bonding layer including a first bonding sub-layer and a second bonding sub-layer, the first bonding sub-layer including a first metal oxide material in an amorphous state and a plurality of metal nanoparticles, the second bonding sub-layer including a second metal oxide material in an amorphous state; forming a second bonding layer on a carrier substrate, the second bonding layer including a third metal oxide material in an amorphous state; conducting a surface modification process on the first and second bonding layers; bonding the device and carrier substrates to each other through the first and second bonding layers; and annealing the first and second bonding layers to convert the first, second, and third metal oxide materials from the amorphous state to a crystalline state.
    Type: Application
    Filed: January 4, 2024
    Publication date: July 10, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Zheng-Yong LIANG, Yu-Yun PENG, Keng-Chu LIN, Wei-Ting YEH, Chia-Yun CHENG, Chen-Hao WU, Yu-Wei LU, Han-De CHEN, Hsu-Kai CHANG, Kuei-Lin CHAN, Kenichi SANO, Huang-Lin CHAO, Cheng-I CHU, Yi-Rui CHEN
  • Patent number: 12336249
    Abstract: A method of forming a semiconductor device includes forming a sacrificial gate structure over a substrate, depositing a spacer layer on the sacrificial gate structure in a conformal manner, performing a multi-step oxidation process to the spacer layer, etching the spacer layer to form gate sidewall spacers on opposite sidewalls of the sacrificial gate structure, removing the sacrificial gate structure to form a trench between the gate sidewalls spacers, and forming a metal gate structure in the trench.
    Type: Grant
    Filed: March 16, 2022
    Date of Patent: June 17, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Rui Chen, Yi-Fan Chen, Szu-Ying Chen, Sen-Hong Syue, Huicheng Chang, Yee-Chia Yeo
  • Publication number: 20240332401
    Abstract: Embodiments include nanostructure devices and methods of forming nanostructure devices which include a treatment process to expand a sidewall spacer material to close a seam in the sidewall spacer material after deposition. The treatment process includes oxidation anneal and heat anneal to expand the sidewall spacer material and crosslink the open seam to form a closed seam, lower k-value, and decrease density.
    Type: Application
    Filed: June 13, 2024
    Publication date: October 3, 2024
    Inventors: Li-Chi Yu, Cheng-I Chu, Chen-Fong Tsai, Yi-Rui Chen, Sen-Hong Syue, Wen-Kai Lin, Yoh-Rong Liu, Huicheng Chang, Yee-Chia Yeo
  • Patent number: 12040382
    Abstract: Embodiments include nanostructure devices and methods of forming nanostructure devices which include a treatment process to expand a sidewall spacer material to close a seam in the sidewall spacer material after deposition. The treatment process includes oxidation anneal and heat anneal to expand the sidewall spacer material and crosslink the open seam to form a closed seam, lower k-value, and decrease density.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: July 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Li-Chi Yu, Cheng-I Chu, Chen-Fong Tsai, Yi-Rui Chen, Sen-Hong Syue, Wen-Kai Lin, Yoh-Rong Liu, Huicheng Chang, Yee-Chia Yeo
  • Publication number: 20230299175
    Abstract: A method of forming a semiconductor device includes forming a sacrificial gate structure over a substrate, depositing a spacer layer on the sacrificial gate structure in a conformal manner, performing a multi-step oxidation process to the spacer layer, etching the spacer layer to form gate sidewall spacers on opposite sidewalls of the sacrificial gate structure, removing the sacrificial gate structure to form a trench between the gate sidewalls spacers, and forming a metal gate structure in the trench.
    Type: Application
    Filed: March 16, 2022
    Publication date: September 21, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Rui CHEN, Yi-Fan CHEN, Szu-Ying CHEN, Sen-Hong SYUE, Huicheng CHANG, Yee-Chia YEO
  • Publication number: 20220262925
    Abstract: Embodiments include nanostructure devices and methods of forming nanostructure devices which include a treatment process to expand a sidewall spacer material to close a seam in the sidewall spacer material after deposition. The treatment process includes oxidation anneal and heat anneal to expand the sidewall spacer material and crosslink the open seam to form a closed seam, lower k-value, and decrease density.
    Type: Application
    Filed: May 17, 2021
    Publication date: August 18, 2022
    Inventors: Li-Chi Yu, Cheng-I Chu, Chen-Fong Tsai, Yi-Rui Chen, Sen-Hong Syue, Wen-Kai Lin, Yoh-Rong Liu, Huicheng Chang, Yee-Chia Yeo
  • Patent number: 10940438
    Abstract: The present invention provides an omniphobic membrane and application thereof. The omniphobic membrane comprises a porous substrate which has a pore size between 0.4 and 2 ?m, a top coat, and an interface layer between the porous substrate and the top coat, and the omniphobic membrane has a carbon/silicon ratio between 40 and 60, and a hierarchical re-entrant structure. Furthermore, both of a process for fabricating the omniphobic membrane and a method for desalination of a liquid by membrane distillation are provided in the present invention.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: March 9, 2021
    Assignee: NATIONAL TAIWAN UNIVERSITY
    Inventors: Kuo-Lun Tung, Allen Huang, Liang-Hsun Chen, Yi-Rui Chen, Chien-Hua Chen, Che-Chen Hsu, Feng-Yu Tsai
  • Publication number: 20200156006
    Abstract: The present invention provides an omniphobic membrane and application thereof. The omniphobic membrane comprises a porous substrate which has a pore size between 0.4 and 2 ?m, a top coat, and an interface layer between the porous substrate and the top coat, and the omniphobic membrane has a carbon/silicon ratio between 40 and 60, and a hierarchical re-entrant structure. Furthermore, both of a process for fabricating the omniphobic membrane and a method for desalination of a liquid by membrane distillation are provided in the present invention.
    Type: Application
    Filed: November 16, 2018
    Publication date: May 21, 2020
    Inventors: Kuo-Lun Tung, Allen Huang, Liang-Hsun Chen, Yi-Rui Chen, Chien-Hua Chen, Che-Chen Hsu, Feng-Yu Tsai