Patents by Inventor Yi-Sern Lai

Yi-Sern Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10450478
    Abstract: The present invention provides an epoxy resin comprising: a polymer having a structure of a reaction product of a monomer of epoxy having at least two epoxide groups per molecule, a polyether monoamine, and an epoxidized oil. The present invention also provides an aqueous dispersion and a water-borne epoxy coating composition which comprise the epoxy resin. The present inventions are low in volatile organic compounds and have enhanced properties such as high hardness, high adhesion strength, high impact resistance and high corrosion resistance.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: October 22, 2019
    Assignee: CHANG CHUN PLASTICS CO., LTD.
    Inventors: Ying-Jui Lin, Liang-Hsing Liu, Yung-Sheng Lin, I-Chiang Lai, Yi-Sern Wong, Kuen-Yuan Hwang
  • Patent number: 10392504
    Abstract: This disclosure relates to reactive epoxy compounds that have high water solubility. The reactive epoxy compounds are obtained by mixing an epoxy resin having at least two epoxy groups per molecule with a carboxyl group-containing compound obtained by reacting a polyetheramine comprising a primary amine and an acid anhydride derived from a polyvalent carboxylic acid. This disclosure also relates to waterborne epoxy resin composition comprising core-shell type epoxy resin particles dispersed in a solvent, wherein the particles are formed by an epoxy resin encapsulated in the reactive epoxy compounds of the present invention. The waterborne epoxy resin composition is low in volatile organic compounds (“VOC”).
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: August 27, 2019
    Assignee: Chang Chun Plastics Co., LTD.
    Inventors: Liang-Hsing Liu, Ying-Jui Lin, Yung-Sheng Lin, I-Chiang Lai, Kuen-Yuan Hwang, Yi-Sern Wong
  • Patent number: 7577833
    Abstract: An IPSec processor is a network security device. It is designed primary for an environment requesting for a throughput of Gigabits per second. By using a new architecture, the parallel processing and pipeline processing become more efficient, thereof higher performance. An IPSec Core in the IPSec processor employs the sharing structure, which raise the utility of the Encryption Engine and Authentication Engine. Moreover, the IPSec Core can be duplicated, allowing a parallel processing. Because the IPSec Core deals with IPSec processing, the Pre_Operation, operation, and post_operation, it becomes a complete set of processing unit and easy for duplicating. In addition, several features have been created for a hardware base implementation, including the processing of the bundled SA case, early verification of the packet, and no need to build an additional context in order to perform a crypto operation.
    Type: Grant
    Filed: May 5, 2006
    Date of Patent: August 18, 2009
    Assignee: Industrial Technology Research Institute
    Inventor: Yi-Sern Lai
  • Publication number: 20060265585
    Abstract: An IPSec processor is a network security device. It is designed primary for an environment requesting for a throughput of Gigabits per second. By using a new architecture, the parallel processing and pipeline processing become more efficient, thereof higher performance. An IPSec Core in the IPSec processor employs the sharing structure, which raise the utility of the Encryption Engine and Authentication Engine. Moreover, the IPSec Core can be duplicated, allowing a parallel processing. Because the IPSec Core deals with IPSec processing, the Pre_Operation, operation, and post_operation, it becomes a complete set of processing unit and easy for duplicating. In addition, several features have been created for a hardware base implementation, including the processing of the bundled SA case, early verification of the packet, and no need to build an additional context in order to perform a crypto operation.
    Type: Application
    Filed: May 5, 2006
    Publication date: November 23, 2006
    Inventor: Yi-Sern Lai
  • Publication number: 20040039936
    Abstract: An IPSec processor is a network security device. It is designed primary for an environment requesting for a throughput of Gigabits per second. By using a new architecture, the parallel processing and pipeline processing become more efficient, thereof higher performance. An IPSec Core in the IPSec processor employs the sharing structure, which raise the utility of the Encryption Engine and Authentication Engine. Moreover, the IPSec Core can be duplicated, allowing a parallel processing. Because the IPSec Core deals with IPSec processing, the Pre_Operation, operation, and post_operation, it becomes a complete set of processing unit and easy for duplicating. In addition, several features have been created for a hardware base implementation, including the processing of the bundled SA case, early verification of the packet, and no need to build an additional context in order to perform a crypto operation.
    Type: Application
    Filed: August 21, 2002
    Publication date: February 26, 2004
    Inventor: Yi-Sern Lai
  • Patent number: 6324286
    Abstract: A full duplex DES cipher processor (DCP) supports to execute sixteen rounds of data encryption standard (DES) operation in four encryption modes and four decryption modes, namely: Electronic Code Book (ECB) mode, Cipher Block Chaining (CBC) mode, Cipher Feedback (CFB) mode, and Output Feedback (OFB) mode for both encryption and decryption. A DCP is composed of an I/O unit, an IV/key storage unit, a control unit, and an algorithm unit. The algorithm unit is used to encrypt/decrypt the incoming text message. The algorithm unit having a crypto engine allows encryption and decryption performed alternately, by sharing the same crypto engine. Since for crypto applications in communication services like T1, E1, V.35, the algorithm unit operation time is much shorter than the data I/O time; in other word, the algorithm unit is in the idle state mostly.
    Type: Grant
    Filed: October 5, 1998
    Date of Patent: November 27, 2001
    Assignee: Industrial Technology Research Institute
    Inventors: Yi-Sern Lai, I-Yao Chuang, Bor-Wen Chiou, Chin-Ning Yang