Abstract: A method for predicting clinical severity of a neurological disorder includes steps of: a) identifying, according to a magnetic resonance imaging (MRI) image of a brain, brain image regions each of which contains a respective portion of diffusion index values of a diffusion index, which results from image processing performed on the MRI image; b) for one of the brain image regions, calculating a characteristic parameter based on the respective portion of the diffusion index values; and c) calculating a severity score that represents the clinical severity of the neurological disorder of the brain based on the characteristic parameter of the one of the brain image regions via a prediction model associated with the neurological disorder.

Abstract: A method for fabricating a semiconductor arrangement is provided. The method includes forming a first dielectric layer and forming a first semiconductive layer over the first dielectric layer. The first semiconductive layer is patterned to form a patterned first semiconductive layer. The first dielectric layer is patterned using the patterned first semiconductive layer to form a patterned first dielectric layer. A second semiconductive layer is formed over the patterned first dielectric layer and the patterned first semiconductive layer.

Abstract: The present disclosure relates to methods, compositions and kits for treating conditions that are related with angiopoietin-like 3 (ANGPTL3) by gene editing.

Abstract: A method for fabricating a semiconductor arrangement is provided. The method includes forming a first dielectric layer and forming a first semiconductive layer over the first dielectric layer. The first semiconductive layer is patterned to form a patterned first semiconductive layer. The first dielectric layer is patterned using the patterned first semiconductive layer to form a patterned first dielectric layer. A second semiconductive layer is formed over the patterned first dielectric layer and the patterned first semiconductive layer.

Abstract: A method includes forming a first fin and a second fin protruding from a substrate; forming an isolation layer surrounding the first fin and the second fin; epitaxially growing a first epitaxial region on the first fin and a second epitaxial region on the second fin, wherein the first epitaxial region and the second epitaxial region are merged together; performing an etching process on the first epitaxial region and the second epitaxial region, wherein the etching process separates the first epitaxial region from the second epitaxial region; depositing a dielectric material between the first epitaxial region and the second epitaxial region; and forming a first gate stack extending over the first fin.

Abstract: A semiconductor device comprising a semiconductor channel, an epitaxial structure coupled to the semiconductor channel, and a gate structure electrically coupled to the semiconductor channel. The semiconductor device further comprises a first interconnect structure electrically coupled to the epitaxial structure and a dielectric layer that contains nitrogen. The dielectric layer comprises a first portion protruding from a nitrogen-containing dielectric capping layer that overlays either the gate structure or the first interconnect structure.

Abstract: A method for fabricating a semiconductor arrangement is provided. The method includes forming a first dielectric layer and forming a first semiconductive layer over the first dielectric layer. The first semiconductive layer is patterned to form a patterned first semiconductive layer. The first dielectric layer is patterned using the patterned first semiconductive layer to form a patterned first dielectric layer. A second semiconductive layer is formed over the patterned first dielectric layer and the patterned first semiconductive layer.

Abstract: A semiconductor structure includes a semiconductor substrate, a metal layer, an interlayer dielectric (ILD) layer. The metal layer is disposed over the semiconductor substrate. The ILD layer is over the semiconductor substrate and laterally surrounding the metal layer, in which the ILD layer has a first portion in contact with a first sidewall of the metal layer and a second portion in contact with a second sidewall of the metal layer opposite to the first sidewall of the metal layer, and a width of the first portion of the ILD layer decreases as a distance from the semiconductor substrate increases.

Abstract: In a method of forming a pattern over a semiconductor substrate, a target layer to be patterned is formed over a substrate, a mask pattern including an opening is formed in a mask layer, a shifting film is formed in an inner sidewall of the opening, a one-directional etching operation is performed to remove a part of the shifting film and a part of the mask layer to form a shifted opening, and the target layer is patterned by using the mask layer with the shifted opening as an etching mask. A location of the shifted opening is laterally shifted from an original location of the opening.

Abstract: A semiconductor structure includes a semiconductor substrate, a metal layer, an interlayer dielectric (ILD) layer. The metal layer is disposed over the semiconductor substrate. The ILD layer is over the semiconductor substrate and laterally surrounding the metal layer, in which the ILD layer has a first portion in contact with a first sidewall of the metal layer and a second portion in contact with a second sidewall of the metal layer opposite to the first sidewall of the metal layer, and a width of the first portion of the ILD layer decreases as a distance from the semiconductor substrate increases.

Abstract: A method is provided. A sacrificial layer is formed over a semiconductor substrate. An etching process is performed to form an opening in the sacrificial layer. The etching process includes a first cycle and a second cycle performed after the first cycle, and each of the first cycle and the second cycle includes applying a passivation gas and an etchant gas over the sacrificial layer, and performing an ionized gas bombardment on the sacrificial layer after applying the passivation gas and the etchant gas over the sacrificial layer. The passivation gas is applied at a first flow rate in the first cycle and is applied at a second flow rate in the second cycle, and the first flow rate is higher than the second flow rate.

Abstract: A method for fabricating a semiconductor arrangement is provided. The method includes forming a first dielectric layer and forming a first semiconductive layer over the first dielectric layer. The first semiconductive layer is patterned to form a patterned first semiconductive layer. The first dielectric layer is patterned using the patterned first semiconductive layer to form a patterned first dielectric layer. A second semiconductive layer is formed over the patterned first dielectric layer and the patterned first semiconductive layer.

Abstract: A method is provided. A sacrificial layer is formed over a semiconductor substrate. An etching process is performed to form an opening in the sacrificial layer. The etching process includes a first cycle and a second cycle performed after the first cycle, and each of the first cycle and the second cycle includes applying a passivation gas and an etchant gas over the sacrificial layer, and performing an ionized gas bombardment on the sacrificial layer after applying the passivation gas and the etchant gas over the sacrificial layer. The passivation gas is applied at a first flow rate in the first cycle and is applied at a second flow rate in the second cycle, and the first flow rate is higher than the second flow rate.

Abstract: A method of forming a semiconductor structure is provided. In this method, a semiconductor substrate is provided. A SoC layer is formed on the semiconductor substrate. A hard mask layer is formed over the SoC layer. The hard mask layer is patterned to expose a portion of the SoC layer. At least one opening is formed on the portion of the SoC layer using an ALE operation, thereby enabling the remaining portion of the SoC layer adjacent to the at least one opening to have a re-entrant angle included between a sidewall of the SoC layer and a bottom of the SoC layer.

Abstract: A storage unit combining module capable of loading a plurality of storage units, and a storage unit moving suit having several storage unit combining modules and a related server apparatus are disclosed. The storage unit combining module includes a base, a circuit backboard and a signal adapter. The base has several positioning zones and an open zone. The circuit backboard includes a first section and a second section bent from each other. The circuit backboard further includes a plurality of connectors respectively disposed on the corresponding positioning zones. The signal adapter is disposed on the open zone and electrically connected to the second section. Two storage units are respectively loaded into two positioning zones on a right side of the base in a first inserting direction, and one storage unit is further loaded into a single positioning zone on a left side of the base in a second inserting direction.

Abstract: A storage unit combining module capable of loading a plurality of storage units, and a storage unit moving suit having several storage unit combining modules and a related server apparatus are disclosed. The storage unit combining module includes a base, a circuit backboard and a signal adapter. The base has several positioning zones and an open zone. The circuit backboard includes a first section and a second section bent from each other. The circuit backboard further includes a plurality of connectors respectively disposed on the corresponding positioning zones. The signal adapter is disposed on the open zone and electrically connected to the second section. Two storage units are respectively loaded into two positioning zones on a right side of the base in a first inserting direction, and one storage unit is further loaded into a single positioning zone on a left side of the base in a second inserting direction.

Abstract: A case includes a housing, a cover and a switch module with a secure mechanism. The case has an accommodation portion. The cover is disposed on the case to have a cover position. The cover covers the accommodation portion. The switch module including a pressing switch and a switch-changing element is located in the accommodation portion and connected to the housing. The switch-changing includes a first pivot part, a pressing part, and a stop part. The first pivot part pivots the housing. The pressing part and the stop part jut from the first pivot part along different radial directions. The switch-changing element has a test position and a non-test position for rotating relative to the housing. When the switch-changing element locates at the test position, a position of the position of the stop part overlaps the cover position.

Abstract: A electronic device includes a chassis, a panel, a cover and a security structure. The panel covers a side of the chassis. The cover covers another side of the chassis. The security structure includes a locking component, a positioning component and a linking shaft. The locking component is disposed on the panel and interfered with the chassis to lock the panel. The positioning component is disposed on the cover and interfered with the chassis to position the cover. The linking shaft is disposed between the locking component and the positioning component and stops the positioning component from being separated from the chassis. When a position of the locking component is adjusted to release the interference between the locking component and the chassis, the linking shaft is driven by the locking component to release the positioning component.

Abstract: A method includes forming a hard mask over a substrate, patterning the hard mask to form a first plurality of trenches, and filling a dielectric material into the first plurality of trenches to form a plurality of dielectric regions. The hard mask is removed from between the plurality of dielectric regions, wherein a second plurality of trenches is left by the removed hard mask. An epitaxy step is performed to grow a semiconductor material in the second plurality of trenches.

Abstract: A storage unit combining module capable of loading a plurality of storage units, and a storage unit moving suit having several storage unit combining modules and a related server apparatus are disclosed. The storage unit combining module includes a base, a circuit backboard and a signal adapter. The base has several positioning zones and an open zone. The circuit backboard includes a first section and a second section bent from each other. The circuit backboard further includes a plurality of connectors respectively disposed on the corresponding positioning zones. The signal adapter is disposed on the open zone and electrically connected to the second section. Two storage units are respectively loaded into two positioning zones on a right side of the base in a first inserting direction, and one storage unit is further loaded into a single positioning zone on a left side of the base in a second inserting direction.