Patents by Inventor Yi-Shan Chen

Yi-Shan Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12230740
    Abstract: A light-emitting device includes a semiconductor stack including a first semiconductor layer, a second semiconductor layer and an active area between the first semiconductor layer and the second semiconductor layer, wherein the first semiconductor layer including an upper surface; an exposed region formed in the semiconductor stack to expose the upper surface; a first protective layer covering the exposed region and a portion of the second semiconductor layer, wherein the first protective layer includes a first part with a first thickness formed on the upper surface and a second part with a second thickness formed on the second semiconductor layer, the first thickness is smaller than the second thickness; a first reflective structure formed on the second semiconductor layer and including one or multiple openings; and a second reflective structure formed on the first reflective structure and electrically connected to the second semiconductor layer through the one or multiple openings.
    Type: Grant
    Filed: April 22, 2021
    Date of Patent: February 18, 2025
    Assignee: EPISTAR CORPORATION
    Inventors: Jhih-Yong Yang, Hsin-Ying Wang, De-Shan Kuo, Chao-Hsing Chen, Yi-Hung Lin, Meng-Hsiang Hong, Kuo-Ching Hung, Cheng-Lin Lu
  • Publication number: 20250043261
    Abstract: The present disclosure relates to methods, compositions and kits for treating conditions that are related with angiopoietin-like 3 (ANGPTL3) by gene editing.
    Type: Application
    Filed: July 11, 2024
    Publication date: February 6, 2025
    Inventors: Yi-Shan Chen, Sandeep Soni, Laura Serwer, Jonathan Terrett, John Kulman
  • Publication number: 20250037858
    Abstract: The present invention disclose a medical image-based system for predicting lesion classification and a method thereof. The system comprises a feature data extracting module for providing a raw feature data based on a medical image, and a predicting module for outputting a predicted class and a risk index according to the raw feature data. The predicting module comprises a classification unit for generating the predicted class and a prediction score corresponding thereto according to the raw feature data, and a risk evaluation unit for generating the risk index according to the prediction score. The system provides medical personnels a reference score and a risk index to determine progression of a certain disease.
    Type: Application
    Filed: February 1, 2024
    Publication date: January 30, 2025
    Inventors: YI-SHAN TSAI, YU-HSUAN LAI, CHENG-SHIH LAI, CHAO-YUN CHEN, MENG-JHEN WU, YI-CHUAN LIN, YI-TING CHIANG, PENG-HAO FANG, PO-TSUN KUO, YI-CHIH CHIU
  • Patent number: 12211212
    Abstract: An image segmentation method includes the following steps: obtaining a target image; inputting the target image into a machine learning model to obtain an image segmentation parameter value corresponding to the target image; executing an image segmentation algorithm on the target image according to the image segmentation parameter value to obtain an image segmentation result, wherein the image segmentation result is segmenting the target image into object regions; and displaying the image segmentation result. In addition, an electronic device and storage medium using the method are also provided.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: January 28, 2025
    Assignee: NATIONAL CHENG KUNG UNIVERSITY
    Inventors: Yi-Shan Tsai, Cheng-Shih Lai, Chao-Yun Chen, Meng-Jhen Wu, Yun-Chiao Wu, Hsin-Yi Feng, Po-Tsun Kuo, Kai-Yi Wang, Wei-Cheng Su
  • Patent number: 12207962
    Abstract: The present invention relates to a method for measuring muscle mass, including: a first selection step, wherein a frame selection information is obtained by using a frame to select a fascia region from a provided computed tomography image under the condition that the window width ranges from 300 HU to 500 HU and the window level ranges from 40 HU to 50 HU, wherein the selected range of the fascia region includes a muscle; and a second selection step, wherein a muscle information of the muscle is obtained by calculating a pixel value in the frame-selected fascia region under the condition that the HU value of the CT image ranges from ?29 HU to 150 HU.
    Type: Grant
    Filed: April 20, 2022
    Date of Patent: January 28, 2025
    Assignee: National Cheng Kung University
    Inventors: Yi-Shan Tsai, Yu-Hsuan Lai, Bow Wang, Cheng-Shih Lai, Chao-Yun Chen, Meng-Jhen Wu, Po-Tsun Kuo, Tsung-Han Lee
  • Publication number: 20250011743
    Abstract: The present disclosure relates to methods, compositions and kits for treating conditions that are related with angiopoietin-like 3 (ANGPTL3) by gene editing.
    Type: Application
    Filed: July 11, 2024
    Publication date: January 9, 2025
    Inventors: Yi-Shan Chen, Sandeep Soni, Laura Serwer, Jonathan Terrett, John Kulman
  • Publication number: 20240363756
    Abstract: A semiconductor device includes: a semiconductor fin extending along a first lateral direction; a gate structure extending along a second lateral direction perpendicular to the first lateral direction and straddling the semiconductor fin; an epitaxial structure disposed in the semiconductor fin and next to the gate structure; a first interconnect structure extending along the second lateral direction and disposed above the epitaxial structure; and a dielectric layer including a first portion and a second portion that form a stair.
    Type: Application
    Filed: June 7, 2024
    Publication date: October 31, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lien Huang, Yi-Shan Chen, Kuan-Da Huang, Han-Yu Lin, Li-Te Lin, Ming-Huan Tsai
  • Patent number: 12046676
    Abstract: A semiconductor device comprising a semiconductor channel, an epitaxial structure coupled to the semiconductor channel, and a gate structure electrically coupled to the semiconductor channel. The semiconductor device further comprises a first interconnect structure electrically coupled to the epitaxial structure and a dielectric layer that contains nitrogen. The dielectric layer comprises a first portion protruding from a nitrogen-containing dielectric capping layer that overlays either the gate structure or the first interconnect structure.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: July 23, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Lien Huang, Yi-Shan Chen, Kuan-Da Huang, Han-Yu Lin, Li-Te Lin, Ming-Huan Tsai
  • Patent number: 12037616
    Abstract: The present disclosure relates to methods, compositions and kits for treating conditions that are related with angiopoietin-like 3 (ANGPTL3) by gene editing.
    Type: Grant
    Filed: February 28, 2023
    Date of Patent: July 16, 2024
    Assignee: CRISPR THERAPEUTICS AG
    Inventors: Yi-Shan Chen, Sandeep Soni, Laura Serwer, Jonathan Terrett, John Kulman
  • Publication number: 20240222134
    Abstract: In a method of forming a pattern over a semiconductor substrate, a target layer to be patterned is formed over a substrate, a mask pattern including an opening is formed in a mask layer, a shifting film is formed in an inner sidewall of the opening, a one-directional etching operation is performed to remove a part of the shifting film and a part of the mask layer to form a shifted opening, and the target layer is patterned by using the mask layer with the shifted opening as an etching mask. A location of the shifted opening is laterally shifted from an original location of the opening.
    Type: Application
    Filed: March 15, 2024
    Publication date: July 4, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Chen LO, Yi-Shan CHEN, Chih-Kai YANG, Pinyen LIN
  • Patent number: 11978640
    Abstract: In a method of forming a pattern over a semiconductor substrate, a target layer to be patterned is formed over a substrate, a mask pattern including an opening is formed in a mask layer, a shifting film is formed in an inner sidewall of the opening, a one-directional etching operation is performed to remove a part of the shifting film and a part of the mask layer to form a shifted opening, and the target layer is patterned by using the mask layer with the shifted opening as an etching mask. A location of the shifted opening is laterally shifted from an original location of the opening.
    Type: Grant
    Filed: April 9, 2021
    Date of Patent: May 7, 2024
    Inventors: Yi-Chen Lo, Yi-Shan Chen, Chih-Kai Yang, Pinyen Lin
  • Patent number: 11901176
    Abstract: A method for fabricating a semiconductor arrangement is provided. The method includes forming a first dielectric layer and forming a first semiconductive layer over the first dielectric layer. The first semiconductive layer is patterned to form a patterned first semiconductive layer. The first dielectric layer is patterned using the patterned first semiconductive layer to form a patterned first dielectric layer. A second semiconductive layer is formed over the patterned first dielectric layer and the patterned first semiconductive layer.
    Type: Grant
    Filed: February 20, 2023
    Date of Patent: February 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Yi-Shan Chen, Hao-Heng Liu
  • Publication number: 20230279376
    Abstract: The present disclosure relates to methods, compositions and kits for treating conditions that are related with angiopoietin-like 3 (ANGPTL3) by gene editing.
    Type: Application
    Filed: February 28, 2023
    Publication date: September 7, 2023
    Inventors: Yi-Shan Chen, Sandeep Soni, Laura Serwer, Jonathan Terrett, John Kulman
  • Publication number: 20230197439
    Abstract: A method for fabricating a semiconductor arrangement is provided. The method includes forming a first dielectric layer and forming a first semiconductive layer over the first dielectric layer. The first semiconductive layer is patterned to form a patterned first semiconductive layer. The first dielectric layer is patterned using the patterned first semiconductive layer to form a patterned first dielectric layer. A second semiconductive layer is formed over the patterned first dielectric layer and the patterned first semiconductive layer.
    Type: Application
    Filed: February 20, 2023
    Publication date: June 22, 2023
    Inventors: Yi-Shan CHEN, Hao-Heng LIU
  • Publication number: 20230155005
    Abstract: A method includes forming a first fin and a second fin protruding from a substrate; forming an isolation layer surrounding the first fin and the second fin; epitaxially growing a first epitaxial region on the first fin and a second epitaxial region on the second fin, wherein the first epitaxial region and the second epitaxial region are merged together; performing an etching process on the first epitaxial region and the second epitaxial region, wherein the etching process separates the first epitaxial region from the second epitaxial region; depositing a dielectric material between the first epitaxial region and the second epitaxial region; and forming a first gate stack extending over the first fin.
    Type: Application
    Filed: May 13, 2022
    Publication date: May 18, 2023
    Inventors: Yu-Lien Huang, Hao-Heng Liu, Po-Chin Chang, Yi-Shan Chen, Ming-Huan Tsai
  • Publication number: 20230067696
    Abstract: A semiconductor device comprising a semiconductor channel, an epitaxial structure coupled to the semiconductor channel, and a gate structure electrically coupled to the semiconductor channel. The semiconductor device further comprises a first interconnect structure electrically coupled to the epitaxial structure and a dielectric layer that contains nitrogen. The dielectric layer comprises a first portion protruding from a nitrogen-containing dielectric capping layer that overlays either the gate structure or the first interconnect structure.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lien Huang, Yi-Shan Chen, Kuan-Da Huang, Han-Yu Lin, Li-Te Lin, Ming-Huan Tsai
  • Patent number: 11587782
    Abstract: A method for fabricating a semiconductor arrangement is provided. The method includes forming a first dielectric layer and forming a first semiconductive layer over the first dielectric layer. The first semiconductive layer is patterned to form a patterned first semiconductive layer. The first dielectric layer is patterned using the patterned first semiconductive layer to form a patterned first dielectric layer. A second semiconductive layer is formed over the patterned first dielectric layer and the patterned first semiconductive layer.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: February 21, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Yi-Shan Chen, Hao-Heng Liu
  • Patent number: 11551966
    Abstract: A semiconductor structure includes a semiconductor substrate, a metal layer, an interlayer dielectric (ILD) layer. The metal layer is disposed over the semiconductor substrate. The ILD layer is over the semiconductor substrate and laterally surrounding the metal layer, in which the ILD layer has a first portion in contact with a first sidewall of the metal layer and a second portion in contact with a second sidewall of the metal layer opposite to the first sidewall of the metal layer, and a width of the first portion of the ILD layer decreases as a distance from the semiconductor substrate increases.
    Type: Grant
    Filed: August 21, 2020
    Date of Patent: January 10, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Shan Chen, Chan-Syun David Yang, Li-Te Lin, Pinyen Lin
  • Publication number: 20220328324
    Abstract: In a method of forming a pattern over a semiconductor substrate, a target layer to be patterned is formed over a substrate, a mask pattern including an opening is formed in a mask layer, a shifting film is formed in an inner sidewall of the opening, a one-directional etching operation is performed to remove a part of the shifting film and a part of the mask layer to form a shifted opening, and the target layer is patterned by using the mask layer with the shifted opening as an etching mask. A location of the shifted opening is laterally shifted from an original location of the opening.
    Type: Application
    Filed: April 9, 2021
    Publication date: October 13, 2022
    Inventors: Yi-Chen LO, Yi-Shan CHEN, Chih-Kai YANG, Pinyen LIN
  • Patent number: RE48588
    Abstract: A storage unit combining module capable of loading a plurality of storage units, and a storage unit moving suit having several storage unit combining modules and a related server apparatus are disclosed. The storage unit combining module includes a base, a circuit backboard and a signal adapter. The base has several positioning zones and an open zone. The circuit backboard includes a first section and a second section bent from each other. The circuit backboard further includes a plurality of connectors respectively disposed on the corresponding positioning zones. The signal adapter is disposed on the open zone and electrically connected to the second section. Two storage units are respectively loaded into two positioning zones on a right side of the base in a first inserting direction, and one storage unit is further loaded into a single positioning zone on a left side of the base in a second inserting direction.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: June 8, 2021
    Assignee: Wistron Corporation
    Inventors: Pei-Lin Huang, Kuen-Lin Lee, Yi-Shan Chen, Kuan-Hsun Lu