Abstract: The present invention provides a memory cell, which includes a substrate, a gate dielectric layer, a patterned material layer, a selection gate and a control gate. The gate dielectric layer is disposed on the substrate. The patterned material layer is disposed on the substrate, wherein the patterned material layer comprises a vertical portion and a horizontal portion. The selection gate is disposed on the gate dielectric layer and atone side of the vertical portion of the patterned material layer. The control gate is disposed on the horizontal portion of the patterned material layer and at another side of the vertical portion, wherein the vertical portion protrudes over a top of the selection gate. The present invention further provides another embodiment of a memory cell and manufacturing methods thereof.

Abstract: A semiconductor structure includes a substrate and a plurality of memory cells disposed on the substrate. Each memory cell includes a gate structure. The gate structures are spaced from each other by a spacing S. Each gate structure includes a dielectric layer and a gate electrode. The dielectric layer has an U-shape and defines an opening toward upside. The gate electrode is disposed in the opening. Each gate structure has a length L. A ratio of S/L is smaller than 1.

Abstract: Provided is a semiconductor device including a memory gate structure and a select gate structure. The memory gate structure is closely adjacent to the select gate structure. Besides, an air gap encapsulated by an insulating layer is disposed between the memory gate structure and the select gate structure.

Abstract: A flash memory structure includes a memory gate on a substrate, a select gate adjacent to the memory gate, and an oxide-nitride spacer between the memory gate and the select gate, where the oxide-nitride spacer further includes an oxide layer and a nitride layer having an upper nitride portion and a lower nitride portion, and the upper nitride portion is thinner than the lower nitride portion.

Abstract: Provided is a semiconductor device including a memory gate structure and a select gate structure. The memory gate structure is closely adjacent to the select gate structure. Besides, an air gap encapsulated by an insulating layer is disposed between the memory gate structure and the select gate structure.

Abstract: A manufacturing method of a semiconductor device includes the following steps. A plurality of select gates are formed on a memory region of a semiconductor substrate. Two charge storage structures are formed between two adjacent select gates. A source region is formed in the semiconductor substrate, and the source region is formed between the two adjacent select gates. An insulation block is formed between the two charge storage structures and formed on the source region. A memory gate is formed on the insulation block, and the memory gate is connected to the two charge storage structures.

Abstract: A flash cell forming process includes the following steps. A first gate is formed on a substrate. A first spacer is formed at a side of the first gate, where the first spacer includes a bottom part and a top part. The bottom part is removed, thereby an undercut being formed. A first selective gate is formed beside the first spacer and fills into the undercut. The present invention also provides a flash cell formed by said flash cell forming process. The flash cell includes a first gate, a first spacer and a first selective gate. The first gate is disposed on a substrate. The first spacer is disposed at a side of the first gate, where the first spacer has an undercut at a bottom part, and therefore exposes the substrate. The first selective gate is disposed beside the first spacer and extends into the undercut.

Abstract: A method for fabricating non-volatile memory device is disclosed. The method includes the steps of: providing a substrate having a stack structure thereon; performing a first oxidation process to form a first oxide layer on the substrate and the stack structure; etching the first oxide layer for forming a first spacer adjacent to the stack structure; performing a second oxidation process to form a second oxide layer on the substrate; forming a dielectric layer on the first spacer and the second oxide layer; and etching the dielectric layer for forming a second spacer.

Abstract: A semiconductor process is described. A semiconductor substrate having a memory area, a first device area and a second device area is provided. A patterned charge-trapping layer is formed on the substrate, covering the memory area and the second device area but exposing the first device area. A first gate oxide layer is formed in the first device area. The charge-trapping layer in the second device area is removed. A second gate oxide layer is formed in the second device area.

Abstract: The present invention provides a method of fabricating a memory structure, especially forming an oxide on top of a spacer to prevent the spacer from being over-etched, the method comprising the steps of: providing a semiconductor substrate; forming a charge trapping layer, a first conducting layer and a capping layer as a gate stack on the substrate; forming a first gate structure by patterning; a plurality of spacers are patterned and disposed adjacent to the sidewall of said gate stack; depositing a second conducting layer on the substrate to cover the first gate structure and the spacer; selectively etching the second conducting layer to expose the top of the spacer; performing an oxidation process to form an oxide on top of the spacer.

Abstract: A flash memory structure includes a memory gate on a substrate, a select gate adjacent to the memory gate, and an oxide-nitride spacer between the memory gate and the select gate, where the oxide-nitride spacer further includes an oxide layer and a nitride layer having an upper nitride portion and a lower nitride portion, and the upper nitride portion is thinner than the lower nitride portion.

Abstract: A semiconductor process is described. A semiconductor substrate having a memory area, a first device area and a second device area is provided. A patterned charge-trapping layer is formed on the substrate, covering the memory area and the second device area but exposing the first device area. A first gate oxide layer is formed in the first device area. The charge-trapping layer in the second device area is removed. A second gate oxide layer is formed in the second device area.

Abstract: The present invention provides a memory cell, which includes a substrate, a gate dielectric layer, a patterned material layer, a selection gate and a control gate. The gate dielectric layer is disposed on the substrate. The patterned material layer is disposed on the substrate, wherein the patterned material layer comprises a vertical portion and a horizontal portion. The selection gate is disposed on the gate dielectric layer and atone side of the vertical portion of the patterned material layer. The control gate is disposed on the horizontal portion of the patterned material layer and at another side of the vertical portion, wherein the vertical portion protrudes over a top of the selection gate. The present invention further provides another embodiment of a memory cell and manufacturing methods thereof.

Abstract: A layout structure for memory devices includes a plurality of first gate patterns, a plurality of first landing pad patterns, a plurality of dummy patterns, a plurality of second landing pad patterns, and a plurality of second gate patterns. The first landing pad patterns are parallel with each other and electrically connected to the first gate patterns. The dummy patterns and the first landing pad patterns are alternately arranged, and the second landing pad patterns are respectively positioned in between one first landing pad pattern and one dummy pattern. The second gate patterns are electrically connected to the second landing pad patterns.

Abstract: A layout structure for memory devices includes a plurality of first gate patterns, a plurality of first landing pad patterns, a plurality of dummy patterns, a plurality of second landing pad patterns, and a plurality of second gate patterns. The first landing pad patterns are parallel with each other and electrically connected to the first gate patterns. The dummy patterns and the first landing pad patterns are alternately arranged, and the second landing pad patterns are respectively positioned in between one first landing pad pattern and one dummy pattern. The second gate patterns are electrically connected to the second landing pad patterns.

Abstract: A locking device for a spline shaft of a brush cutter is disclosed. The brush cutter comprises the spline shaft installed in a shell and coupled with a driven bevel gear that is coupled with a drive bevel gear, which is further linked to a power device. The spline shaft has a blind hole, and the shell has a stub tube facing to the blind hole. A spring and a pin are received in the stub tube in such a way that the pin is inserted through the spring and the spring acts on the pin. With this structure, when a cutting tool is to be assembled to or disassembled from the spline shaft, it is only needed to push the pin into the blind hole of the spline shaft to restrain the spline shaft from rotating. Accordingly, the cutting tool can be assembled or disassembled in safe and convenient.

Abstract: A locking device for a spline shaft of a brush cutter is disclosed. The brush cutter comprises the spline shaft installed in a shell and coupled with a driven bevel gear that is coupled with a drive bevel gear, which is linked to a power device. The locking device comprises a collar having a notch and fixed on the spline shaft. The shell has a stub tube facing to the notch. A spring and a pin are received in the stub tube in such a way that the pin is inserted through the spring and the spring acts on the pin. When a cutting tool is to be assembled to or disassembled from the spline shaft, it is only needed to push the pin into the notch of the collar to restrain the spline shaft from rotating. Accordingly, the cutting tool can be assembled or disassembled in safe and convenient.