Patents by Inventor Yi-Shao Lai
Yi-Shao Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10056325Abstract: The present disclosure relates to a semiconductor package and a manufacturing method thereof. The semiconductor package includes a semiconductor element including a main body, a plurality of conductive vias, and at least one filler. The conductive vias penetrate through the main body. The filler is located in the main body, and a coefficient of thermal expansion (CTE) of the filler is different from that of the main body and the conductive vias. Thus, the CTE of the overall semiconductor element can be adjusted, so as to reduce warpage.Type: GrantFiled: January 19, 2017Date of Patent: August 21, 2018Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chin-Li Kao, Chang-Chi Lee, Yi-Shao Lai
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Publication number: 20170133311Abstract: The present disclosure relates to a semiconductor package and a manufacturing method thereof The semiconductor package includes a semiconductor element including a main body, a plurality of conductive vias, and at least one filler. The conductive vias penetrate through the main body. The filler is located in the main body, and a coefficient of thermal expansion (CTE) of the filler is different from that of the main body and the conductive vias. Thus, the CTE of the overall semiconductor element can be adjusted, so as to reduce warpage.Type: ApplicationFiled: January 19, 2017Publication date: May 11, 2017Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chin-Li KAO, Chang-Chi LEE, Yi-Shao LAI
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Patent number: 9589840Abstract: The present disclosure relates to a semiconductor package and a manufacturing method thereof. The semiconductor package includes a semiconductor element including a main body, a plurality of conductive vias, and at least one filler. The conductive vias penetrate through the main body. The filler is located in the main body, and a coefficient of thermal expansion (CTE) of the filler is different from that of the main body and the conductive vias. Thus, the CTE of the overall semiconductor element can be adjusted, so as to reduce warpage.Type: GrantFiled: May 9, 2014Date of Patent: March 7, 2017Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chin-Li Kao, Chang-Chi Lee, Yi-Shao Lai
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Publication number: 20140332957Abstract: The present disclosure relates to a semiconductor package and a manufacturing method thereof The semiconductor package includes a semiconductor element including a main body, a plurality of conductive vias, and at least one filler. The conductive vias penetrate through the main body. The filler is located in the main body, and a coefficient of thermal expansion (CTE) of the filler is different from that of the main body and the conductive vias. Thus, the CTE of the overall semiconductor element can be adjusted, so as to reduce warpage.Type: ApplicationFiled: May 9, 2014Publication date: November 13, 2014Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chin-Li KAO, Chang-Chi LEE, Yi-Shao LAI
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Patent number: 8592982Abstract: A semiconductor package includes a semiconductor structure. The semiconductor structure includes a plurality of dielectric layers and a plurality of conductive interconnects embedded in the semiconductor structure. The semiconductor structure also includes a plurality of proximity communication signal input terminals. At least one of the plurality of proximity communication signal input terminals includes a first electrode and a second electrode. The first electrode and the second electrode are spaced apart so as to be configured to provide proximity communication through capacitive coupling. The first electrode is exposed proximate to a surface of the semiconductor structure.Type: GrantFiled: October 4, 2011Date of Patent: November 26, 2013Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Yi-Shao Lai, Tsung-Yueh Tsai, Ming-Kun Chen, Tai-Ping Wang, Ming-Hsiang Cheng
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Patent number: 8421242Abstract: A semiconductor package is provided. The semiconductor package includes an organic substrate, a stiffness layer, and a chip subassembly. The stiffness layer is formed on the organic substrate. The chip subassembly is disposed on the stiffness layer. The chip subassembly includes at least a first chip, a second chip, and a third chip. The second chip is disposed between the first chip and the third chip in a stacked orientation. The first chip, the second chip, and the third chip have the function of proximity communication.Type: GrantFiled: December 31, 2009Date of Patent: April 16, 2013Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Hsiao-Chuan Chang, Tsung-Yueh Tsai, Yi-Shao Lai, Chang-Lin Yeh, Ming-Hsiang Cheng
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Patent number: 8368216Abstract: The present invention relates to a semiconductor package having at least one first layer chip, a plurality of first metal bumps, at least one second layer chip and a package body. The first layer chip includes a first active surface upon which the first metal bumps are disposed and a plurality of first signal coupling pads disposed adjacent to the first active surface. The second layer chip is electrically connected to the first layer chip, and includes a second active surface that faces the first active surface and a plurality of second signal coupling pads. The second signal coupling pads are capacitively coupled to the first signal coupling pads so as to provide proximity communication between the first layer chip and the second layer chip. The package body encapsulates the first layer chip, the first metal bumps, and the second layer chip, and the first metal bumps are partially exposed.Type: GrantFiled: August 31, 2010Date of Patent: February 5, 2013Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Yi-Shao Lai, Tsung-Yueh Tsai, Ming-Kun Chen, Hsiao-Chuan Chang, Ming-Hsiang Cheng
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Patent number: 8274149Abstract: A semiconductor device package and a method of fabricating the same are disclosed. The semiconductor device package includes a substrate, a buffer structure, two active chips and a bridge chip. The substrate has a cavity, a first surface and a second surface opposite to the first surface. The cavity is extended from the first surface toward the second surface, and the buffer structure is disposed in the cavity. The active chips are disposed on and electrically connected to the first surface and around the cavity. The active chips both have a first active surface. The bridge chip is disposed in the cavity and above the buffer structure. The bridge chip has a second active surface, the second active surface faces the first active surfaces and is partially overlapped with the first active surfaces, the bridge chip is used for providing a proximity communication between the active chips.Type: GrantFiled: March 29, 2010Date of Patent: September 25, 2012Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Hsiao-Chuan Chang, Tsung-Yueh Tsai, Yi-Shao Lai, Ming-Hsiang Cheng
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Patent number: 8253431Abstract: The present invention relates to an apparatus and a method for testing non-contact pads of a semiconductor device to be tested. The apparatus includes an insulating body, at least one testing module and a plurality of probes. The insulating body includes an accommodating cavity, a lower opening and at least one side opening. The side opening communicates with the accommodating cavity and the lower opening. The testing module is disposed in the side opening, and each testing module includes a circuit board and an active chip. The active chip is disposed on and electrically connected to the circuit board. The active chip has a plurality of testing pads exposed to the accommodating cavity. The probes are disposed in the lower opening.Type: GrantFiled: May 20, 2010Date of Patent: August 28, 2012Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Yi-Shao Lai, Tsung-Yueh Tsai, Ming-Kun Chen, I. L. Lin, Ken Juang, Ming-Hsiang Cheng
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Patent number: 8222726Abstract: A semiconductor device package and a method of fabricating the same are provided. The semiconductor device package includes a substrate, a first chip, a jumper chip, a plurality of first bonding wires and a plurality of second bonding wires. The substrate has a plurality of contact pads. The first chip is disposed and electrically connected to the substrate via the first bonding wires. The jumper chip is disposed on the first chip and has a plurality of metal pads. Each of the metal pads is electrically connected to two contact pads of the substrate via two second bonding wires, respectively.Type: GrantFiled: March 29, 2010Date of Patent: July 17, 2012Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Hsiao-Chuan Chang, Tsung-Yueh Tsai, Yi-Shao Lai, Jiunn Chen, Ming-Hsiang Cheng
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Patent number: 8222733Abstract: A first substrate has a first surface facing a second surface of the second substrate. The active chips are disposed on and electrically connected to the first surface, and spaced apart from each other by an interval, wherein the active chips respectively have a first active surface. The bridge chip is mechanically and electrically connected to the second surface, and has a second active surface partially overlapped with the first active surfaces of the active chips, such that the bridge chip is used for providing a proximity communication between the active chips. The connection structure is disposed between the first surface and the second surface for combining the first substrate and the second substrate.Type: GrantFiled: March 22, 2010Date of Patent: July 17, 2012Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Ming-Hsiang Cheng, Yi-Shao Lai, Tsung-Yueh Tsai, Hsiao-Chuan Chang
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Publication number: 20120153489Abstract: A semiconductor package includes a semiconductor structure. The semiconductor structure includes a plurality of dielectric layers and a plurality of conductive interconnects embedded in the semiconductor structure. The semiconductor structure also includes a plurality of proximity communication signal input terminals. At least one of the plurality of proximity communication signal input terminals includes a first electrode and a second electrode. The first electrode and the second electrode are spaced apart so as to be configured to provide proximity communication through capacitive coupling. The first electrode is exposed proximate to a surface of the semiconductor structure.Type: ApplicationFiled: October 4, 2011Publication date: June 21, 2012Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: YI-SHAO LAI, TSUNG-YUEH TSAI, MING-KUN CHEN, TAI-PING WANG, MING-HSIANG CHENG
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Publication number: 20120119342Abstract: The advanced quad flat non-leaded package structure includes a carrier, a chip, a plurality of wires, and a molding compound. The carrier includes a die pad and a plurality of leads. The inner leads of the leads are designed to possess incurved sidewalls for enhancing the adhesion between the inner leads and the surrounding molding compound.Type: ApplicationFiled: November 11, 2010Publication date: May 17, 2012Applicants: MediaTek Inc., ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Pao-Huei Chang Chien, Ping-Cheng Hu, Po-Shing Chiang, Wei-Lun Cheng, Hsueh-Te Wang, Hsiao-Chuan Chang, Tsung-Yueh Tsai, Yi-Shao Lai, Ping-Feng Yang
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Publication number: 20120091575Abstract: The present invention relates to a semiconductor package and a method for making the same. The semiconductor package includes a substrate, at least one first chip, a dielectric layer and at least one second chip. The first chip is attached and electrically connected to the substrate. The first chip includes a first active surface and a plurality of first signal coupling pads. The first signal coupling pads are disposed adjacent to the first active surface. The dielectric layer is disposed on the first active surface. The second chip is attached and electrically connected to the substrate by metal bumps. The second chip includes a second active surface and a plurality of second signal coupling pads. The second active surface contacts the dielectric layer. The second signal coupling pads are disposed adjacent to the second active surface, and capacitively coupled to the first signal coupling pads of the first chip, so as to provide proximity communication between the first chip and the second chip.Type: ApplicationFiled: October 15, 2010Publication date: April 19, 2012Inventors: Yi-Shao Lai, Tsung-Yueh Tsai, Ming-Kun Chen, Hsiao-Chuan Chang, Ming-Hsiang Cheng
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Publication number: 20120049360Abstract: The present invention relates to a semiconductor package and a method for making the same. The semiconductor package includes at least one first layer chip, a plurality of first metal bumps, at least one second layer chip and a package body. The first layer chip includes a first active surface and a plurality of first signal coupling pads. The first signal coupling pads are disposed adjacent to the first active surface. The first metal bumps are disposed on the first active surface of the first layer chip. The second layer chip is electrically connected to the first layer chip, and includes a second active surface and a plurality of second signal coupling pads. The second active surface faces the first active surface of the first layer chip. The second signal coupling pads are disposed adjacent to the second active surface, and capacitively coupled to the first signal coupling pads of the first layer chip, so as to provide proximity communication between the first layer chip and the second layer chip.Type: ApplicationFiled: August 31, 2010Publication date: March 1, 2012Inventors: Yi-Shao Lai, Tsung-Yueh Tsai, Ming-Kun Chen, Hsiao-Chuan Chang, Ming-Hsiang Cheng
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Patent number: 8115285Abstract: A semiconductor package and related methods are described. In one embodiment, the package includes a die pad, multiple leads, a chip, a package body, and a protective layer. The die pad includes an upper sloped portion, a lower sloped portion, and a peripheral edge region defining a cavity with a cavity bottom. Each lead includes an upper sloped portion and a lower sloped portion. The chip is disposed on the cavity bottom and is coupled to the leads. The package body is formed over the chip and the leads, substantially fills the cavity, and substantially covers the upper sloped portions of the die pad and the leads. The lower sloped portions of the die pad and the leads at least partially extend outwardly from a lower surface of the package body. The protective layer substantially covers the lower sloped portion and the lower surface of at least one lead.Type: GrantFiled: August 15, 2008Date of Patent: February 14, 2012Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Chien-Wen Chen, Yi-Shao Lai, Hsiao-Chuan Chang, Tsung-Yueh Tsai, Pao-Huei Chang Chien, Ping-Cheng Hu, Hsu-Yang Lee
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Patent number: 8110931Abstract: A wafer defines a plurality of chips arranged in array manner. Each chip includes at least one aluminum pad and a middle material. The middle material covers the aluminum pad and is mounted on the aluminum pad.Type: GrantFiled: July 10, 2009Date of Patent: February 7, 2012Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Hsiao Chuan Chang, Tsung Yueh Tsai, Yi Shao Lai, Ho Ming Tong, Jian Cheng Chen, Wei Chi Yih, Chang Ying Hung, Cheng Wei Huang, Chih Hsing Chen, Tai Yuan Huang, Chieh Ting Chen, Yi Tsai Lu
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Publication number: 20110309516Abstract: The present invention relates to a semiconductor package and a method for making the same. The semiconductor package includes a first chip and a second chip. The first chip comprises a first active surface, at least one first non-top metal layer and a plurality of first signal coupling pads. The first non-top metal layer is disposed adjacent to and spaced apart from the first active surface by a second distance. The first signal coupling pads are disposed on the first non-top metal layer. The second chip is electrically connected to the first chip. The second chip comprises a second active surface, at least one second non-top metal layer and a plurality of third signal coupling pads. The second active surface faces the first active surface of the first chip. The second non-top metal layer is disposed adjacent to and spaced apart from the second active surface by a fourth distance.Type: ApplicationFiled: June 21, 2010Publication date: December 22, 2011Inventors: Yi-Shao Lai, Tsung-Yueh Tsai, Ming-Kun Chen, Hsiao-Chuan Chang, Ming-Hsiang Cheng
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Patent number: 8076786Abstract: A wire bonding structure includes a chip and a bonding wire. The chip includes a base material, at least one first metallic pad, a re-distribution layer and at least one second metallic pad. The first metallic pad is disposed on the base material. The re-distribution layer has a first end and a second end, and the first end is electrically connected to the first metallic pad. The second metallic pad is electrically connected to the second end of the re-distribution layer. The bonding wire is bonded to the second metallic pad.Type: GrantFiled: July 13, 2009Date of Patent: December 13, 2011Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Chang Ying Hung, Hsiao Chuan Chang, Tsung Yueh Tsai, Yi Shao Lai, Jian Cheng Chen, Wei Chi Yih, Ho Ming Tong
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Publication number: 20110298139Abstract: The present invention relates to a semiconductor package. The semiconductor package includes a substrate, a first chip and a second chip. The substrate has a first surface, a second surface and at least one through hole. The first chip is disposed adjacent to the first surface of the substrate. The first chip includes a first active surface and a plurality of first signal pads. Part of the first active surface is exposed to the through hole. The position of the first signal pads corresponds to the through hole. The second chip is disposed adjacent to the second surface. The second chip includes a second active surface and a plurality of second signal pads. Part of the second active surface is exposed to the through hole. The position of the second signal pads corresponds to the through hole, and the second signal pads are capacitively coupled to the first signal pads of the first chip, so as to provide proximity communication between the first chip and the second chip.Type: ApplicationFiled: June 4, 2010Publication date: December 8, 2011Inventors: Yi-Shao Lai, Tsung-Yueh Tsai, Ming-Kun Chen, Hsiao-Chuan Chang, Ming-Hsiang Cheng