Abstract: A method of producing a chip scale package is disclosed. The method includes dicing a wafer into a plurality of chip arrays, each array including two or more integrated circuit chips. The method further includes mounting each array on a substrate and dicing each array, attached to the substrate, into individual chip scale packages, each individual chip scale package including only one integrated circuit chip.

Abstract: A semiconductor package with a semiconductor chip having under bump metallizations (UBMs) on a first surface and a substrate having open vias. The substrate is attached to the semiconductor chip with the UBMs in alignment with the open vias. An encapsulant surrounds the semiconductor chip and the substrate and a conductor fills the open vias to form external package connections. A method of forming a semiconductor package having external package connections includes providing a semiconductor chip having under bump metallizations (UBMs) on a first surface; attaching the first surface of the semiconductor chip to a substrate, the UBMs of the semiconductor chip being in alignment with open vias formed in the substrate; encapsulating the semiconductor chip and the substrate; and filling with open vias with a conductor to form the external package connections.

Abstract: A semiconductor chip package and method of making the same. A first chip unit includes a first substrate and a first IC chip electrically connected to the first substrate. A second chip unit includes a second substrate and a second IC chip electronically connected to the second substrate. An adhesive material is provided on a surface of the first IC chip and the second chip unit is mounted onto the surface of the first chip unit including the adhesive material so that at least a portion of the second structure is encapsulated by the adhesive material, thereby providing some encapsulation in the same step as mounting. The first chip unit and the second chip unit may be separated by a spacer which may also provide an electrical connection.

Abstract: A semiconductor package includes a plurality of first leads, each with a top outer portion removed from the lead and an outer end, and a plurality of second leads, each with a bottom outer portion removed from the lead and an outer end. The first and second leads alternate with each other along an edge of the package. Also, the outer ends of the first leads form a first row along the edge of the package and the outer ends of the second leads form a second row along the edge of the package. In one embodiment, the first and second rows are parallel to each other and an encapsulant covers at least a portion of the first and second leads.

Abstract: A semiconductor package includes a plurality of first leads, each with a top outer portion removed from the lead and an outer end, and a plurality of second leads, each with a bottom outer portion removed from the lead and an outer end. The first and second leads alternate with each other along an edge of the package. Also, the outer ends of the first leads form a first row along the edge of the package and the outer ends of the second leads form a second row along the edge of the package. In one embodiment, the first and second rows are parallel to each other and an encapsulant covers at least a portion of the first and second leads.

Abstract: A thermally enhanced ball grid array package is disclosed. The package includes a base layer element and a flip chip die mounted on the base layer element. The die has a first surface electrically coupled to the base layer element, a second surface opposite to the first surface, and lateral sides. A molding compound encapsulates the base layer element and the lateral sides of the die. A surface is formed of the second surface of the die and an upper surface of the molding compound. A material is disposed on the surface, and a heat spreader is mounted on the material.

Abstract: An integrated circuit package having a die pad with a first face and a second face, a plurality of inner leads, and a plurality of sides between the first face and the second face. The plurality of inner leads is disposed substantially co-planer with and substantially around the die pad. The package also comprises a plurality of outer leads disposed substantially co-planar with and substantially around the plurality of inner leads and the die pad, so that the sides of each of the plurality of outer leads are offset from the sides of each of the plurality of inner leads. A first adhesive layer disposed on the first face of the die pad and a second adhesive layer disposed on the first faces of each of the plurality of inner leads. An IC chip is coupled to the first face of the die pad through the first adhesive layer and to the plurality of inner leads through the second adhesive layer. The package further comprises wires linking the inner leads and outer leads to the IC chip.

Abstract: An integrated circuit package is disclosed. The package comprises a plurality of leads, each lead having a first face and a second face opposite to the first face. The package also comprises a die pad having a first face and a second face opposite to the first face. The second face of the die pad is orthogonally offset from the second face of the leads so that the second face of the die pad and the second face of the leads are not coplanar. The package also comprises an integrated circuit chip substantially laterally disposed between the plurality of leads, and having a first face and a second face opposite to the first face. The first face of the integrated circuit chip is proximate to the second face of the die pad and the first face of the integrated circuit chip is coupled to the second face of the die pad. The package further comprises a plurality of wires that link the plurality of leads to the integrated circuit chip.

Abstract: This invention includes a heat sink structure for use in a semiconductor package that includes a ring structure with down sets and a heat sink connected to the ring structure. The down sets can be slanted or V-shaped. The invention also includes a method of manufacturing a semiconductor package that includes inserting a substrate with an attached semiconductor chip in a first mold portion, placing a heat sink structure on top of a portion of the substrate, placing a mold release film onto a second mold portion, clamping a second mold portion onto a portion of the heat sink structure, injecting an encapsulant into a mold cavity, wherein the encapsulant surrounds portions of the substrate, semiconductor chip and heat sink structure, curing the encapsulant, whereby the heat sink structure adheres to the encapsulant and singulating the encapsulated assembly to form a semiconductor package.

Abstract: A BGA package is disclosed including a base IC structure having a base substrate, with an opening running length-wise there through. A first semiconductor chip is mounted face-down on the base substrate so the bond pads thereof are accessible through the opening. The package also includes a secondary IC structure including a secondary substrate, having an opening running there through, and a second semiconductor chip. The second chip is mounted face-down on the secondary substrate so that the bond pads thereof are accessible through the opening in the secondary substrate. An encapsulant fills the opening in the secondary substrate and forms a substantially planar surface over the underside of the secondary substrate. The substantially planar surface is mounted to the first chip of the base IC structure through an adhesive. Wires connect a conductive portion of the secondary IC structure to a conductive portion of the base IC structure.

Abstract: A semiconductor chip package and method of making the same. A first chip unit includes a first substrate and a first IC chip electrically connected to the first substrate. A second chip unit includes a second substrate and a second IC chip electronically connected to the second substrate. An adhesive material is provided on a surface of the first IC chip and the second chip unit is mounted onto the surface of the first chip unit including the adhesive material so that at least a portion of the second structure is encapsulated by the adhesive material, thereby providing some encapsulation in the same step as mounting. The first chip unit and the second chip unit may be separated by a spacer which may also provide an electrical connection.

Abstract: An integrated circuit package having a die pad with a first face and a second face, a plurality of inner leads, and a plurality of sides between the first face and the second face. The plurality of inner leads is disposed substantially co-planer with and substantially around the die pad. The package also comprises a plurality of outer leads disposed substantially co-planar with and substantially around the plurality of inner leads and the die pad, so that the sides of each of the plurality of outer leads are offset from the sides of each of the plurality of inner leads. A first adhesive layer disposed on the first face of the die pad and a second adhesive layer disposed on the first faces of each of the plurality of inner leads. An IC chip is coupled to the first face of the die pad through the first adhesive layer and to the plurality of inner leads through the second adhesive layer. The package further comprises wires linking the inner leads and outer leads to the IC chip.

Abstract: Two substrates each carrying MEMS or MOEMS structures are bonded face to face and interconnected to form a compact surface-mountable package.

Abstract: A MEMS/MOEMS device is provided on a first substrate which is bonded to a second substrate to form a package. Interconnections may be provided via the second substrate and an hermetic seal may be formed to protect the MEMS/MOEMS device from outgassing.

Abstract: An integrated circuit package is disclosed. The package comprises a plurality of leads, each lead having a first face and a second face opposite to the first face. The package also comprises a die pad having a first face and a second face opposite to the first face. The second face of the die pad is orthogonally offset from the second face of the leads so that the second face of the die pad and the second face of the leads are not coplanar. The package also comprises an integrated circuit chip substantially laterally disposed between the plurality of leads, and having a first face and a second face opposite to the first face. The first face of the integrated circuit chip is proximate to the second face of the die pad and the first face of the integrated circuit chip is coupled to the second face of the die pad. The package further comprises a plurality of wires that link the plurality of leads to the integrated circuit chip.

Abstract: An integrated circuit package having a die pad with a first face and a second face, a plurality of inner leads, and a plurality of sides between the first face and the second face. The plurality of inner leads is disposed substantially co-planer with and substantially around the die pad. The package also comprises a plurality of outer leads disposed substantially co-planar with and substantially around the plurality of inner leads and the die pad, so that the sides of each of the plurality of outer leads are offset from the sides of each of the plurality of inner leads. A first adhesive layer disposed on the first face of the die pad and a second adhesive layer disposed on the first faces of each of the plurality of inner leads. An IC chip is coupled to the first face of the die pad through the first adhesive layer and to the plurality of inner leads through the second adhesive layer. The package further comprises wires linking the inner leads and outer leads to the IC chip.