Abstract: A motion synchronized multi-tier pallet rack and a battery formation apparatus are provided. The pallet rack includes a fixation rack, two movable frames, and two actuators. The movable frames are coupled to two corresponding sides of the fixation rack and each includes telescopic arms, a motor, and a drive rod. The actuators are disposed on other the two corresponding sides of the fixation rack to drive the movable frames to move toward or away from each other. The telescopic arms are kinematically connected to the motor through the drive rod to extend from or retract into the movable frame. The battery formation apparatus includes a motion synchronized multi-tier pallet rack, a conveyor module, a formation cabinet, and a controller. The conveyor module carries a battery module. The controller controls the pallet rack to obtain the battery module from the conveyor module and place the battery module in the formation cabinet.

Abstract: A power supply unit supplies power to a load, and the power supply unit includes a power factor corrector, a DC conversion module, and an isolated conversion module. The power factor corrector is plugged into a first main circuit board and converts an AC power into a DC power. The DC conversion module is plugged into the first main circuit board and converts the DC power into a main power. The isolated conversion module includes a bus capacitor, the bus capacitor is coupled to the DC conversion module through a first power copper bar, and coupled to the power factor corrector through a second power copper bar. The first power copper bar and the second power copper bar are arranged on a side opposite to the first main circuit board, and are arranged in parallel with the first main circuit board.

Abstract: A semiconductor die package includes an inductor-capacitor (LC) semiconductor die that is directly bonded with a logic semiconductor die. The LC semiconductor die includes inductors and capacitors that are integrated into a single die. The inductors and capacitors of the LC semiconductor die may be electrically connected with transistors and other logic components on the logic semiconductor die to form a voltage regulator circuit of the semiconductor die package. The integration of passive components (e.g., the inductors and capacitors) of the voltage regulator circuit into a single semiconductor die reduces signal propagation distances in the voltage regulator circuit, which may increase the operating efficiency of the voltage regulator circuit, may reduce the formfactor for the semiconductor die package, may reduce parasitic capacitance and/or may reduce parasitic inductance in the voltage regulator circuit (thereby improving the performance of the voltage regulator circuit), among other examples.

Abstract: A memory device includes a plurality of arrays coupled in parallel with each other. A first array of the plurality of arrays includes a first switch and a plurality of first memory cells that are arranged in a first column, a second switch and a plurality of second memory cells that are arranged in a second column, and at least one data line coupled to the plurality of first memory cells and the plurality of second memory cells. The second switch is configured to output a data signal from the at least one data line to a sense amplifier.

Abstract: A memory device includes a programming transistor and a reading transistor of an anti-fuse memory cell. The programming transistor includes first semiconductor nanostructures vertically spaced apart from one another, each of the first semiconductor nanostructures having a first width along a first lateral direction. The reading transistor includes second semiconductor nanostructures vertically spaced apart from one another, each of the second semiconductor nanostructures having a second width different from the first width along the second direction. The memory device also includes a first and a second gate metals. The first gate metal wraps around each of the first semiconductor nanostructures with a first gate dielectric disposed therein. The second gate metal wraps around each of the second semiconductor nanostructures with a second gate dielectric disposed therein.

Abstract: A semiconductor device according to embodiments of the present disclosure includes a first die including a first bonding layer and a second die including a second hybrid bonding layer. The first bonding layer includes a first dielectric layer and a first metal coil embedded in the first dielectric layer. The second bonding layer includes a second dielectric layer and a second metal coil embedded in the second dielectric layer. The second hybrid bonding layer is bonded to the first hybrid bonding layer such that the first dielectric layer is bonded to the second dielectric layer and the first metal coil is bonded to the second metal coil.

Abstract: Various embodiments of the present disclosure are directed towards a trench capacitor with a trench pattern for yield improvement. The trench capacitor is on a substrate and comprises a plurality of capacitor segments. The capacitor segments extend into the substrate according to the trench pattern and are spaced with a pitch on an axis. The plurality of capacitor segments comprises an edge capacitor segment at an edge of the trench capacitor and a center capacitor segment at a center of the trench capacitor. The edge capacitor segment has a greater width than the center capacitor segment and/or the pitch is greater at the edge capacitor segment than at the center capacitor segment. The greater width may facilitate stress absorption and the greater pitch may increase substrate rigidity at the edge of the trench capacitor where thermal expansion stress is greatest, thereby reducing substrate bending and trench burnout for yield improvements.

Abstract: A method for managing cache space between one electronic device and multiple storage devices includes identifying and quantifying storage devices connected to an electronic device, and acquiring efficiency information of each identified storage device on preset occasions. Cache space of each storage device is computed on being connected to or being disconnected from the electronic device, taking account of information acquired as to efficiency and quantity of each of the storage devices. A core switch of the electronic device is controlled to allocate a computed cache space to a storage device.

Abstract: An electronic device able to re-initialize following a failed initialization has a processor, a first storage device, and a second storage device. The processor receives storage information stored at the first storage device and sets a plurality of storage parameters of the first storage device, according to the storage information, and re-initializing the first storage device based on the storage parameters. When the initialization fails, the processor adjusts the storage parameters of the first storage device and re-initializes the first storage device based on the adjusted storage parameters.

Abstract: A method for managing cache space between one electronic device and multiple storage devices includes identifying and quantifying storage devices connected to an electronic device, and acquiring efficiency information of each identified storage device on preset occasions. Cache space of each storage device is computed on being connected to or being disconnected from the electronic device, taking account of information acquired as to efficiency and quantity of each of the storage devices. A core switch of the electronic device is controlled to allocate a computed cache space to a storage device.

Abstract: An electronic device able to re-initialize following a failed initialization has a processor, a first storage device, and a second storage device. The processor receives storage information stored at the first storage device and sets a plurality of storage parameters of the first storage device, according to the storage information, and re-initializing the first storage device based on the storage parameters. When the initialization fails, the processor adjusts the storage parameters of the first storage device and re-initializes the first storage device based on the adjusted storage parameters.

Abstract: A circulation apparatus for agricultural and fishery production and irrigation is provided with a water supply device; a production device; a filter device; an irrigation device; a water storage device; and pipes for connecting the water supply device, the production device, the filter device, the irrigation device, and the water storage device together. The water filter device is filtered and sterilized, and outputs to the irrigation device to supply an irrigation water source for agricultural uses. Excess of the irrigation water source outputs to the water storage device for storage, and flows into the water supply device again or the irrigation device so as to make the irrigation water source to be continuously re-circulated and reused among the water supply device, the production device, the filter device, the irrigation device, and the water storage device.

Abstract: A system and method for semiconductor CP (circuit probe) test management. A control request message is received from a client computer, directing alignment of a probe unit or a wafer in a prober, attachment of a probe pin of the probe unit on a specific area of the wafer, and subsequent execution of CP testing. At least one control command corresponding to the control request message is issued to direct the prober for alignment of the probe unit or the wafer, attachment of the probe pin of the probe unit on the specific area of the wafer, and subsequent execution of CP testing.

Abstract: A system and method for semiconductor CP (circuit probe) test management. A control request message is received from a client computer, directing alignment of a probe unit or a wafer in a prober, attachment of a probe pin of the probe unit on a specific area of the wafer, and subsequent execution of CP testing. At least one control command corresponding to the control request message is issued to direct the prober for alignment of the probe unit or the wafer, attachment of the probe pin of the probe unit on the specific area of the wafer, and subsequent execution of CP testing.

Abstract: A system and method thereof for test time forecasting. The system comprises a storage device and a first program module. The storage device stores Circuit Probing (CP) test records individually storing information regarding a test time and a yield of a test unit corresponding to a test program. The first program module receives the CP test records and generates a new test time forecast model according to the CP test records. The new test time forecast model determines a dependent variable corresponding to the test time by utilizing an independent variable corresponding to the yield.