Abstract: An illumination module is provided. The illumination module includes a light-emitting unit. The light-emitting unit includes a light-emitting element array and a focusing lens array. The light-emitting element array includes a plurality of light-emitting elements. The light-emitting elements are used for generating a plurality of light beams. The focusing lens array includes a plurality of focusing lenses. Each of the light-emitting elements corresponds to at least one of the focusing lenses.

Abstract: The current disclosure describes techniques of protecting a metal interconnect structure from being damaged by subsequent chemical mechanical polishing processes used for forming other metal structures over the metal interconnect structure. The metal interconnect structure is receded to form a recess between the metal interconnect structure and the surrounding dielectric layer. A metal cap structure is formed within the recess. An upper portion of the dielectric layer is strained to include a tensile stress which expands the dielectric layer against the metal cap structure to reduce or eliminate a gap in the interface between the metal cap structure and the dielectric layer.

Abstract: A method includes forming a first multilayer interconnect structure over a first side of a device layer, forming a first portion of a second multilayer interconnect structure under a second side of the device layer, forming a trench that extends through the second dielectric layer, the device layer, and the first dielectric layer, forming a conductive structure in the trench, and forming a second portion of the second multilayer interconnect structure under the first portion of the second multilayer interconnect structure. The second portion of the second multilayer interconnect structure includes patterned metal layers disposed in a third dielectric layer, and wherein one or more of the patterned metal layers are in electrical connection with the conductive structure.

Abstract: Disclosed herein are related to a memory array including one-time programmable (OTP) cells. In one aspect, the memory array includes a set of OTP cells including a first subset of OTP cells connected between a first program control line and a first read control line. Each OTP cell of the first subset of OTP cells may include a programmable storage device and a switch connected between the first program control line and the first read control line. The first program control line may extend towards a first side of the memory array along a first direction, and the first read control line may extend towards a second side of the memory array facing away from the first side of the memory array.

Abstract: A microsphere includes a cross-linked hydrophilic substrate, a lipophilic substrate, and a surfactant. The cross-linked hydrophilic substrate includes cross-linked sodium alginate and gelatin. The lipophilic substrate includes iodized oil, C16-C18 alkyl alcohol, and polycaprolactone. The surfactant includes polyoxyethylene stearate. The microsphere is dry or substantially solid. Prior to being used for embolization, the microsphere can be immersed in a drug containing mixture to allow the microsphere to absorb the mixture and expand, thereby loaded with the drug. A method for preparing the microsphere and a method for embolizing tumor in a subject by using the microsphere are also provided.

Abstract: Embodiments herein beneficially enable simultaneous processing of a plurality of substrates in a digital direct write lithography processing system. In one embodiment a method of processing a plurality of substrate includes positioning a plurality of substrates on a substrate carrier of a processing system, positioning the substrate carrier under the plurality of optical modules, independently leveling each of the plurality of substrates, determining offset information for each of the plurality of substrates, generating patterning instructions based on the offset information for each of the plurality of substrates, and patterning each of the plurality of substrates using the plurality of optical modules. The processing system comprises a base, a motion stage disposed on the base, the substrate carrier disposed on the motion stage, a bridge disposed above a surface of the base and separated therefrom, and a plurality of optical modules disposed on the bridge.

Abstract: Embodiments herein beneficially enable simultaneous processing of a plurality of substrates in a digital direct write lithography processing system. In one embodiment a method of processing a plurality of substrate includes positioning a plurality of substrates on a substrate carrier of a processing system, positioning the substrate carrier under the plurality of optical modules, independently leveling each of the plurality of substrates, determining offset information for each of the plurality of substrates, generating patterning instructions based on the offset information for each of the plurality of substrates, and patterning each of the plurality of substrates using the plurality of optical modules. The processing system comprises a base, a motion stage disposed on the base, the substrate carrier disposed on the motion stage, a bridge disposed above a surface of the base and separated therefrom, and a plurality of optical modules disposed on the bridge.

Abstract: Embodiments of the present disclosure generally provide a digital lithography system that can process both large area substrates as well as semiconductor device substrates, such as wafers. Both the large area substrates and the semiconductor device substrates can be processed in the same system simultaneously. Additionally, the system can accommodate different levels of exposure for forming the features over the substrates. For example, the system can accommodate very precise feature patterning as well as less precise feature patterning. The different exposures can occur in the same chamber simultaneously. Thus, the system is capable of processing both semiconductor device substrates and large area substrates simultaneously while also accommodating very precise feature patterning simultaneous with less precise feature patterning.

Abstract: Embodiments of the present disclosure generally provide a digital lithography system that can process both large area substrates as well as semiconductor device substrates, such as wafers. Both the large area substrates and the semiconductor device substrates can be processed in the same system simultaneously. Additionally, the system can accommodate different levels of exposure for forming the features over the substrates. For example, the system can accommodate very precise feature patterning as well as less precise feature patterning. The different exposures can occur in the same chamber simultaneously. Thus, the system is capable of processing both semiconductor device substrates and large area substrates simultaneously while also accommodating very precise feature patterning simultaneous with less precise feature patterning.

Abstract: The disclosure provides nanostructured composites of graphene derivatives and metal nanocrystals for gas storage and gas separation.

Abstract: A semiconductor device including a light sensing region disposed on a substrate is provided that includes a bond structure having one or more patterned layers underlying the pad element. The pad element may be coupled to the light sensing region and may be formed in a first metal layer disposed on the substrate. A second metal layer of the device has a first bond region, a region of the second metal layer that underlies the pad element. This first bond region of the second metal layer includes a pattern of a plurality of conductive lines interposed by dielectric. A via connects the pad element and the second metal layer.

Abstract: A current detection circuit includes a first detection circuit, a second detection circuit, and a control selection circuit. The first detection circuit electrically connects between an input terminal and an output terminal and outputs a first detection signal. The second detection circuit electrically connects between the input terminal and the output terminal and outputs a second detection signal. The control selection circuit electrically connects the output terminal, the first detection circuit, and the second detection circuit and selects one of the first and second detection signals as a detection signal.

Abstract: A semiconductor image sensor device having a conformal protective layer includes a semiconductor substrate a pixel-array region and a peripheral region. The conformal protective layer is disposed over a plurality of pixels having a photodiode and a plurality of transistors in the pixel-array region. Contacts to the plurality of transistors are surrounded by the conformal protective layer. In some embodiments, the conformal protective layer is the same material as transistor gate spacers in the peripheral region.

Abstract: A DC-DC converter includes a zero current detector. The DC-DC converter includes a high-side switch and a low-side switch. When the DC-DC converter works in a discontinuous conduction mode (DCM). The zero current detector detects a zero current a detection node which is arranged between the high-side switch and the low-side switch generates the zero current, the zero current detector outputs the control signal to a driver. The driver switches the high-side switch and the low-side switch off simultaneously according to the control signal.

Abstract: A current detection circuit includes a first detection circuit, a second detection circuit, and a control selection circuit. The first detection circuit electrically connects between an input terminal and an output terminal and outputs a first detection signal. The second detection circuit electrically connects between the input terminal and the output terminal and outputs a second detection signal. The control selection circuit electrically connects the output terminal, the first detection circuit, and the second detection circuit and selects one of the first and second detection signals as a detection signal.

Abstract: A DC-DC converter includes a zero current detector. The DC-DC converter includes a high-side switch and a low-side switch. When the DC-DC converter works in a discontinuous conduction mode (DCM). The zero current detector detects a zero current a detection node which is arranged between the high-side switch and the low-side switch generates the zero current, the zero current detector outputs the control signal to a driver. The driver switches the high-side switch and the low-side switch off simultaneously according to the control signal. The zero current detector includes a temperature compensation unit to control a responsivity of the zero current detector which not influenced by temperature change.

Abstract: A semiconductor image sensor device having a conformal protective layer includes a semiconductor substrate a pixel-array region and a peripheral region. The conformal protective layer is disposed over a plurality of pixels having a photodiode and a plurality of transistors in the pixel-array region. Contacts to the plurality of transistors are surrounded by the conformal protective layer. In some embodiments, the conformal protective layer is the same material as transistor gate spacers in the peripheral region.

Abstract: An image sensor comprises an image sensing substrate that in turns includes an image sensing device, a first sensor pixel, a second sensor pixel, and a divider. The divider is between the first sensor pixel and the second sensor pixel.

Abstract: A DC-DC converter includes a zero current detector. The DC-DC converter includes a high-side switch and a low-side switch. When the DC-DC converter works in a discontinuous conduction mode (DCM). The zero current detector detects a zero current a detection node which is arranged between the high-side switch and the low-side switch generates the zero current, the zero current detector outputs the control signal to a driver. The driver switches the high-side switch and the low-side switch off simultaneously according to the control signal. The zero current detector includes a temperature compensation unit to control a responsivity of the zero current detector which not influenced by temperature change.

Abstract: A DC-DC converter includes a zero current detector. The DC-DC converter includes a high-side switch and a low-side switch. When the DC-DC converter works in a discontinuous conduction mode (DCM). The zero current detector detects a zero current a detection node which is arranged between the high-side switch and the low-side switch generates the zero current, the zero current detector outputs the control signal to a driver. The driver switches the high-side switch and the low-side switch off simultaneously according to the control signal.