Patents by Inventor Yi-Sheng Liu

Yi-Sheng Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240140765
    Abstract: An overhead hoist transfer apparatus includes a rail assembly including a straight rail having an empty section, and a curved rail having a curved empty section; an engine including a first LSD having first and second wheels at two sides respectively; and a second LSD having third and fourth wheels at two sides respectively; a moving carriage driven by the engine and suspended from the rail assembly; first and second guide wheels disposed on the first LSD; third and fourth guide wheels disposed on the second LSD; and two guide boards disposed above a joining point of the straight rail and the curved rail. An elevation of the guide boards is equal to that of the guide wheels. The guide board includes a straight edge and a curved edge.
    Type: Application
    Filed: September 27, 2023
    Publication date: May 2, 2024
    Inventors: Jung-Chieh Chang, Yi-Sheng Chen, Jen-Yung Hsiao, Chia-Fu Hsiao, Wei-Qi Lao, Chen-Chih Chan, Caung-Yu Liu
  • Publication number: 20240145494
    Abstract: An image sensor structure including a substrate, a first pixel structure, a second pixel structure, a dielectric layer, and a conductive layer stack is provided. The first pixel structure includes a first light sensing device. The second pixel structure includes a second light sensing device. The conductive layer stack includes conductive layers. The conductive layer stack has a first opening and a second opening. The first opening is located directly above the first light sensing device and passes through the conductive layers. The second opening is located directly above the second light sensing device and passes through the conductive layers. The second minimum width of the second opening is smaller than the first minimum width of the first opening. The luminous flux of the second pixel structure is different from the luminous flux of the first pixel structure.
    Type: Application
    Filed: November 22, 2022
    Publication date: May 2, 2024
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Ju-Sheng Lu, Yi-Ting Wang, Ming-Chan Liu
  • Publication number: 20240136346
    Abstract: A semiconductor die package includes an inductor-capacitor (LC) semiconductor die that is directly bonded with a logic semiconductor die. The LC semiconductor die includes inductors and capacitors that are integrated into a single die. The inductors and capacitors of the LC semiconductor die may be electrically connected with transistors and other logic components on the logic semiconductor die to form a voltage regulator circuit of the semiconductor die package. The integration of passive components (e.g., the inductors and capacitors) of the voltage regulator circuit into a single semiconductor die reduces signal propagation distances in the voltage regulator circuit, which may increase the operating efficiency of the voltage regulator circuit, may reduce the formfactor for the semiconductor die package, may reduce parasitic capacitance and/or may reduce parasitic inductance in the voltage regulator circuit (thereby improving the performance of the voltage regulator circuit), among other examples.
    Type: Application
    Filed: April 17, 2023
    Publication date: April 25, 2024
    Inventors: Chien Hung LIU, Yu-Sheng CHEN, Yi Ching ONG, Hsien Jung CHEN, Kuen-Yi CHEN, Kuo-Ching HUANG, Harry-HakLay CHUANG, Wei-Cheng WU, Yu-Jen WANG
  • Publication number: 20240116707
    Abstract: A powered industrial truck includes a lateral movement assembly including four sliding members and four pivotal members both on a wheeled carriage, four links having a first end pivotably secured to the sliding member and a second end pivotably secured to either end of the pivotal member, a motor shaft having two ends pivotably secured to the pivotal members respectively, a first electric motor on one frame member, and four mounts attached to the sliding members respectively; two lift assemblies including a second electric motor, a shaft having two ends rotatably secured to the sliding members respectively, two gear trains at the ends of the shaft respectively, a first gear connected to the second electric motor, a second gear on the shaft, and a first roller chain on the first and second gears; two electric attachments on the platform and being laterally moveable, each attachment. The mount has rollers.
    Type: Application
    Filed: September 21, 2023
    Publication date: April 11, 2024
    Inventors: Jung-Chieh Chang, Yi-Sheng Chen, Jen-Yung Hsiao, Chia-Fu Hsiao, Wei-Qi Lao, Chen-Chih Chan, Chung-Yu Liu
  • Patent number: 11955201
    Abstract: A memory device includes a plurality of arrays coupled in parallel with each other. A first array of the plurality of arrays includes a first switch and a plurality of first memory cells that are arranged in a first column, a second switch and a plurality of second memory cells that are arranged in a second column, and at least one data line coupled to the plurality of first memory cells and the plurality of second memory cells. The second switch is configured to output a data signal from the at least one data line to a sense amplifier.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: April 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Meng-Sheng Chang, Chia-En Huang, Yi-Ching Liu, Yih Wang
  • Patent number: 11955554
    Abstract: A method of fabrication of a multi-gate semiconductor device that includes providing a fin having a plurality of a first type of epitaxial layers and a plurality of a second type of epitaxial layers. The plurality of the second type of epitaxial layers is oxidized in the source/drain region. A first portion of a first layer of the second type of epitaxial layers is removed in a channel region of the fin to form an opening between a first layer of the first type of epitaxial layer and a second layer of the first type of epitaxial layer. A portion of a gate structure is then formed in the opening.
    Type: Grant
    Filed: July 15, 2022
    Date of Patent: April 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Huan-Sheng Wei, Hung-Li Chiang, Chia-Wen Liu, Yi-Ming Sheu, Zhiqiang Wu, Chung-Cheng Wu, Ying-Keung Leung
  • Patent number: 11955865
    Abstract: A three-axis voice coil motor including a base, a spherical bearing, a magnetic component, an X-coil group, a Y-coil group, and at least one Z-coil group is provided. The base has a supporting pole. The spherical bearing is rotatably sleeved around the supporting pole. The magnetic component is securely sleeved around the spherical bearing and the magnetic component rotates along with the spherical bearing. The X-coil group is disposed around the magnetic component along an X-axial direction passing through the spherical bearing, and the X-coil group has first gaps. The Y-coil group is disposed around the magnetic component along a Y-axial direction passing through the spherical bearing, and the Y-coil group has second gaps. The Z-coil group is disposed around the magnetic component along a Z-axial direction passing through the spherical bearing.
    Type: Grant
    Filed: October 19, 2021
    Date of Patent: April 9, 2024
    Assignee: National Cheng-Kung University
    Inventors: Chien-Sheng Liu, Yi-Hsuan Lin, Chiu-Nung Yeh
  • Patent number: 11934480
    Abstract: A circuit for in-memory multiply-and-accumulate functions includes a plurality of NAND blocks. A NAND block includes an array of NAND strings, including B columns and S rows, and L levels of memory cells. W word lines are coupled to (B*S) memory cells in respective levels in the L levels. A source line is coupled to the (B*S) NAND strings in the block. String select line drivers supply voltages to connect NAND strings on multiple string select lines to corresponding bit lines simultaneously. Word line drivers are coupled to apply word line voltages to a word line or word lines in a selected level. A plurality of bit line drivers apply input data to the B bit lines simultaneously. A current sensing circuit is coupled to the source line.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: March 19, 2024
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Hang-Ting Lue, Hung-Sheng Chang, Yi-Ching Liu
  • Publication number: 20240085718
    Abstract: An optical element driving mechanism is provided. The optical element driving mechanism includes a movable portion used for connecting an optical element, a fixed portion, and a driving assembly used for driving the movable portion to move relative to the fixed portion. The movable portion is movable relative to the fixed portion.
    Type: Application
    Filed: September 7, 2023
    Publication date: March 14, 2024
    Inventors: Po-Xiang ZHUANG, Chen-Hung CHAO, Yen-Sheng LIU, Shou-Jen LIU, Yi-Ho CHEN, Yung-Hsien YEH
  • Publication number: 20240088026
    Abstract: A semiconductor device according to embodiments of the present disclosure includes a first die including a first bonding layer and a second die including a second hybrid bonding layer. The first bonding layer includes a first dielectric layer and a first metal coil embedded in the first dielectric layer. The second bonding layer includes a second dielectric layer and a second metal coil embedded in the second dielectric layer. The second hybrid bonding layer is bonded to the first hybrid bonding layer such that the first dielectric layer is bonded to the second dielectric layer and the first metal coil is bonded to the second metal coil.
    Type: Application
    Filed: January 17, 2023
    Publication date: March 14, 2024
    Inventors: Yi Ching Ong, Wei-Cheng Wu, Chien Hung Liu, Harry-Haklay Chuang, Yu-Sheng Chen, Yu-Jen Wang, Kuo-Ching Huang
  • Publication number: 20240077745
    Abstract: An optical element driving mechanism is provided. The optical element driving mechanism includes a movable portion used for connecting an optical element, a fixed portion, and a driving assembly used for driving the movable portion to move relative to the fixed portion. The movable portion is movable relative to the fixed portion.
    Type: Application
    Filed: September 7, 2023
    Publication date: March 7, 2024
    Inventors: Po-Xiang ZHUANG, Chen-Hung CHAO, Yen-Sheng LIU, Shou-Jen LIU, Yi-Ho CHEN, Yung-Hsien YEH
  • Publication number: 20210228766
    Abstract: A microsphere includes a cross-linked hydrophilic substrate, a lipophilic substrate, and a surfactant. The cross-linked hydrophilic substrate includes cross-linked sodium alginate and gelatin. The lipophilic substrate includes iodized oil, C16-C18 alkyl alcohol, and polycaprolactone. The surfactant includes polyoxyethylene stearate. The microsphere is dry or substantially solid. Prior to being used for embolization, the microsphere can be immersed in a drug containing mixture to allow the microsphere to absorb the mixture and expand, thereby loaded with the drug. A method for preparing the microsphere and a method for embolizing tumor in a subject by using the microsphere are also provided.
    Type: Application
    Filed: May 31, 2018
    Publication date: July 29, 2021
    Applicants: T-ACE Medical Co., Ltd., T-ACE Medical Co., Ltd.
    Inventors: CHIH HONG CHEN, CHAU NAN HONG, CYUN JHE YAN, CHUEH KUAN WANG, CHEN HSI CHOU, YI SHENG LIU, HONG MING TSAI, CHI MING HO, CHUAN SHENG LIN, XI ZHANG LIN
  • Patent number: 10928743
    Abstract: Embodiments herein beneficially enable simultaneous processing of a plurality of substrates in a digital direct write lithography processing system. In one embodiment a method of processing a plurality of substrate includes positioning a plurality of substrates on a substrate carrier of a processing system, positioning the substrate carrier under the plurality of optical modules, independently leveling each of the plurality of substrates, determining offset information for each of the plurality of substrates, generating patterning instructions based on the offset information for each of the plurality of substrates, and patterning each of the plurality of substrates using the plurality of optical modules. The processing system comprises a base, a motion stage disposed on the base, the substrate carrier disposed on the motion stage, a bridge disposed above a surface of the base and separated therefrom, and a plurality of optical modules disposed on the bridge.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: February 23, 2021
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Chien-Hua Lai, Chia-Hung Kao, Hsiu-Jen Wang, Shih-Hao Kuo, Yi-Sheng Liu, Shih-Hsien Lee, Ching-Chang Chen, Tsu-Hui Yang
  • Publication number: 20190369499
    Abstract: Embodiments herein beneficially enable simultaneous processing of a plurality of substrates in a digital direct write lithography processing system. In one embodiment a method of processing a plurality of substrate includes positioning a plurality of substrates on a substrate carrier of a processing system, positioning the substrate carrier under the plurality of optical modules, independently leveling each of the plurality of substrates, determining offset information for each of the plurality of substrates, generating patterning instructions based on the offset information for each of the plurality of substrates, and patterning each of the plurality of substrates using the plurality of optical modules. The processing system comprises a base, a motion stage disposed on the base, the substrate carrier disposed on the motion stage, a bridge disposed above a surface of the base and separated therefrom, and a plurality of optical modules disposed on the bridge.
    Type: Application
    Filed: March 19, 2019
    Publication date: December 5, 2019
    Inventors: Chien-Hua LAI, Chia-Hung KAO, Hsiu-Jen WANG, Shih-Hao KUO, Yi-Sheng LIU, Shih-Hsien LEE, Ching-Chang CHEN, Tsu-Hui YANG
  • Patent number: 10459341
    Abstract: Embodiments of the present disclosure generally provide a digital lithography system that can process both large area substrates as well as semiconductor device substrates, such as wafers. Both the large area substrates and the semiconductor device substrates can be processed in the same system simultaneously. Additionally, the system can accommodate different levels of exposure for forming the features over the substrates. For example, the system can accommodate very precise feature patterning as well as less precise feature patterning. The different exposures can occur in the same chamber simultaneously. Thus, the system is capable of processing both semiconductor device substrates and large area substrates simultaneously while also accommodating very precise feature patterning simultaneous with less precise feature patterning.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: October 29, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Chien-Hua Lai, Ching-Chang Chen, Shih-Hao Kuo, Tsu-Hui Yang, Hsiu-Jen Wang, Yi-Sheng Liu, Chia-Hung Kao
  • Publication number: 20190235389
    Abstract: Embodiments of the present disclosure generally provide a digital lithography system that can process both large area substrates as well as semiconductor device substrates, such as wafers. Both the large area substrates and the semiconductor device substrates can be processed in the same system simultaneously. Additionally, the system can accommodate different levels of exposure for forming the features over the substrates. For example, the system can accommodate very precise feature patterning as well as less precise feature patterning. The different exposures can occur in the same chamber simultaneously. Thus, the system is capable of processing both semiconductor device substrates and large area substrates simultaneously while also accommodating very precise feature patterning simultaneous with less precise feature patterning.
    Type: Application
    Filed: December 11, 2018
    Publication date: August 1, 2019
    Inventors: Chien-Hua Lai, Ching-Chang Chen, Shih-Hao Kuo, Tsu-Hui Yang, Hsiu-Jen Wang, Yi-Sheng Liu, Chia-Hung Kao
  • Publication number: 20180185814
    Abstract: The disclosure provides nanostructured composites of graphene derivatives and metal nanocrystals for gas storage and gas separation.
    Type: Application
    Filed: May 6, 2016
    Publication date: July 5, 2018
    Inventors: Jeffrey J. Urban, Eun Seon Cho, Felix Raoul Fischer, Anne M. Ruminski, Shaul Aloni, Yi-Sheng Liu, Jinghua Guo, Ryan Cloke, Tomas Marangoni, Cameron Rogers
  • Patent number: 9768221
    Abstract: A semiconductor device including a light sensing region disposed on a substrate is provided that includes a bond structure having one or more patterned layers underlying the pad element. The pad element may be coupled to the light sensing region and may be formed in a first metal layer disposed on the substrate. A second metal layer of the device has a first bond region, a region of the second metal layer that underlies the pad element. This first bond region of the second metal layer includes a pattern of a plurality of conductive lines interposed by dielectric. A via connects the pad element and the second metal layer.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: September 19, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shang-Yen Wu, I-Chih Chen, Yi-Sheng Liu, Volume Chien, Fu-Tsun Tsai, Chi-Cherng Jeng, Ying-Hao Chen
  • Patent number: 9568935
    Abstract: A current detection circuit includes a first detection circuit, a second detection circuit, and a control selection circuit. The first detection circuit electrically connects between an input terminal and an output terminal and outputs a first detection signal. The second detection circuit electrically connects between the input terminal and the output terminal and outputs a second detection signal. The control selection circuit electrically connects the output terminal, the first detection circuit, and the second detection circuit and selects one of the first and second detection signals as a detection signal.
    Type: Grant
    Filed: September 2, 2015
    Date of Patent: February 14, 2017
    Assignee: Fitipower Integrated Technology, Inc.
    Inventors: Chih-Ho Lin, Wen-Yen Lee, Yi-Sheng Liu, Chio-Yi Ho
  • Patent number: 9473719
    Abstract: A semiconductor image sensor device having a conformal protective layer includes a semiconductor substrate a pixel-array region and a peripheral region. The conformal protective layer is disposed over a plurality of pixels having a photodiode and a plurality of transistors in the pixel-array region. Contacts to the plurality of transistors are surrounded by the conformal protective layer. In some embodiments, the conformal protective layer is the same material as transistor gate spacers in the peripheral region.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: October 18, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Volume Chien, Yi-Sheng Liu, Chia-Yu Wei, Yun-Wei Cheng, Chi-Cherng Jeng