Abstract: A method for fabricating oxide layers with different thicknesses on a substrate is described. A field oxide layer is formed on the substrate to define a first active region and a second active region therebetween. A first oxide layer is formed over the first active region. A thin oxynitride layer is formed on the first oxide layer.

Abstract: A method for fabricating oxide layers with different thicknesses on a substrate is described. A field oxide layer is formed on the substrate to define a first active region and a second active region therebetween. A first oxide layer is formed over the first active region. A thin oxynitride layer is formed on the first oxide layer.

Abstract: A fabrication process of forming a semiconductor device with elevated source/drain regions on a substrate is disclosed. The elevated portion of the source/drain regions is provided as a reactant for a later metallization process, thereby preventing the consumption of too much silicon contained in the source/drain regions. First, an elevated silicon layer is formed on portions of a substrate for forming source/drain regions of a semiconductor device. Next, a gate dielectric layer and a gate electrode layer are formed on the elevated silicon layer successively to construct a gate structure. Then, a lightly doped ion implantation process, a process of forming a sidewall spacer and a heavily doped ion implantation process are performed successively. Thus, the elevated silicon layer can be used as a reactant while performing a self-aligned silicidization process.

Abstract: A method for forming self-aligned raised source and drain regions on a semiconductor wafer includes the steps of defining a substrate, growing a first layer of dielectric material over the substrate, depositing a layer of polysilicon over the first layer of dielectric material, patterning and forming at least one gate, depositing a second layer of dielectric material over the gate and the first dielectric layer and masking the second dielectric layer to define a source region and a drain region. The method also includes the steps of anisotropically etching to form sidewall spacers contiguous with the gate, collimated sputtering to deposit a layer of silicon, and implanting ions into the deposited silicon.

Abstract: A floating gate E.sup.2 PROM cell is provided with a poly silicon floating gate having a pointed, sloped edge. A poly oxide is disposed on the pointed, sloped edge of the floating gate. A select gate is disposed on the poly oxide. The select gate overlaps the pointed, sloped edge of the floating gate. The floating gate, poly oxide, and select gate cooperate so that electrons tunnel according to enhanced Fowler Nordheim tunnelling from a point of the pointed, sloped edge of the floating gate, through the poly oxide and into the select gate.A simple process is also provided for fabricating an E.sup.2 PROM cell including the step of forming a nitride layer on a poly silicon layer. The nitride layer is patterned, using a photo-lithographic technique, to form an exposed poly silicon layer surface window. The exposed surface window of the poly silicon layer is then oxidized using a LOCOS (local oxidation of silicon) process to form a poly oxide region.