Patents by Inventor Yi-Shiang Chang

Yi-Shiang Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9508138
    Abstract: A method for detecting photolithographic hotspots is disclosed. After receiving layout data, an aerial image simulation is conducted to extract aerial image intensity indices. Based on the combination of one or more aerial image intensity indices, various aerial image detectors are generated. The value of aerial image detectors is verified to determine the position and type of the photolithographic hotspots.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: November 29, 2016
    Assignee: Powerchip Technology Corporation
    Inventors: Yi-Shiang Chang, Chia-Chi Lin, Shin-Shing Yeh, Pei-Shan Shih, Jun-Cheng Lai
  • Publication number: 20160321793
    Abstract: A method for detecting photolithographic hotspots is disclosed. After receiving layout data, an aerial image simulation is conducted to extract aerial image intensity indices. Based on the combination of one or more aerial image intensity indices, various aerial image detectors are generated. The value of aerial image detectors is verified to determine the position and type of the photolithographic hotspots.
    Type: Application
    Filed: June 18, 2015
    Publication date: November 3, 2016
    Inventors: Yi-Shiang Chang, Chia-Chi Lin, Shin-Shing Yeh, Pei-Shan Shih, Jun-Cheng Lai
  • Publication number: 20160035733
    Abstract: A NAND flash circuit structure includes two select gates disposed on a substrate, and an even number of spaced-apart word lines disposed between the two select gates. The select gate is provided with a first portion and a second portion. The thickness of the first portion and the second portion are different.
    Type: Application
    Filed: October 12, 2015
    Publication date: February 4, 2016
    Inventors: Shu-Cheng Lin, Zih-Song Wang, Yi-Shiang Chang
  • Patent number: 9196623
    Abstract: A semiconductor circuit structure and process of making the same is provided in the present invention, comprising the steps of providing a substrate having a target layer and a hard mask layer, forming a patterned small core body group and a large core body group on the hard mask layer, forming a spacer material layer conformally on the substrate and the core body groups, forming filling bodies in each recess of the spacer material layer, performing a first etching process to remove exposed spacer material layer, using the filling bodies as a mask to perform a second etching process for patterning the hard mask layer, and using the patterned hard mask layer as a mask to perform a third etching process for patterning the conductive layer.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: November 24, 2015
    Assignee: Powerchip Technology Corporation
    Inventors: Shu-Cheng Lin, Zih-Song Wang, Yi-Shiang Chang
  • Publication number: 20140255829
    Abstract: A mask for dual tone development including a opening pattern region and a partial transparent pattern is provided. The opening pattern region includes a plurality of transparent patterns and a plurality of opaque patterns, and a plurality of opening patterns is defined in a photoresist for dual tone development by the transparent patterns and the opaque patterns. The partial transparent pattern surrounds the opening pattern region.
    Type: Application
    Filed: May 17, 2013
    Publication date: September 11, 2014
    Applicant: Powerchip Technology Corporation
    Inventors: Yi-Shiang Chang, Chia-Chi Lin, Hung-Ming Lin
  • Patent number: 8709946
    Abstract: A method for forming contact holes includes following steps. A substrate including a dense region and an isolation region is provided. A material layer is formed on the substrate. Sacrificed patterns are formed on the material layer in the dense region, wherein there is a first opening between the two adjacent sacrificed patterns. A spacer is formed on each of two sides of each of the sacrificed patterns, wherein the spacers are separated from each other. The sacrificed patterns are removed to form a second opening between two adjacent spacers. A planar layer is formed to fill up the second openings. A first slit is formed in the planar layer, wherein the first slit exposes a portion of the material layer under the second openings. The portion of the material layer exposed by the first slit is removed to form third openings in the material layer.
    Type: Grant
    Filed: February 1, 2012
    Date of Patent: April 29, 2014
    Assignee: Powerchip Technology Corporation
    Inventors: Meng-Feng Tsai, Yi-Shiang Chang, Chia-Chi Lin, I-Hsin Chen, Chia-Ming Wu
  • Publication number: 20130264622
    Abstract: A semiconductor circuit structure and process of making the same is provided in the present invention, comprising the steps of providing a substrate having a target layer and a hard mask layer, forming a patterned small core body group and a large core body group on the hard mask layer, forming a spacer material layer conformally on the substrate and the core body groups, forming filling bodies in each recess of the spacer material layer, performing a first etching process to remove exposed spacer material layer, using the filling bodies as a mask to perform a second etching process for patterning the hard mask layer, and using the patterned hard mask layer as a mask to perform a third etching process for patterning the conductive layer.
    Type: Application
    Filed: September 5, 2012
    Publication date: October 10, 2013
    Inventors: Shu-Cheng Lin, Zih-Song Wang, Yi-Shiang Chang
  • Publication number: 20130137270
    Abstract: A method for forming contact holes includes following steps. A substrate including a dense region and an isolation region is provided. A material layer is formed on the substrate. Sacrificed patterns are formed on the material layer in the dense region, wherein there is a first opening between the two adjacent sacrificed patterns. A spacer is formed on each of two sides of each of the sacrificed patterns, wherein the spacers are separated from each other. The sacrificed patterns are removed to form a second opening between two adjacent spacers. A planar layer is formed to fill up the second openings. A first slit is formed in the planar layer, wherein the first slit exposes a portion of the material layer under the second openings. The portion of the material layer exposed by the first slit is removed to form third openings in the material layer.
    Type: Application
    Filed: February 1, 2012
    Publication date: May 30, 2013
    Applicant: POWERCHIP TECHNOLOGY CORPORATION
    Inventors: Meng-Feng Tsai, Yi-Shiang Chang, Chia-Chi Lin, I-Hsin Chen, Chia-Ming Wu
  • Publication number: 20100060871
    Abstract: An off-axis light source is described, including an X-dipole illumination pattern, a Y-dipole illumination pattern and a quadrupole illumination pattern at the illumination surface thereof, wherein the illumination area of the quadrupole illumination pattern is smaller than that of the X- or Y-dipole illumination pattern. A light screen plate is also described, having corresponding openings therein and can be used to form the above off-axis light source. A method of defining different types of patterns with a single exposure is also described, which utilizes the above off-axis light source.
    Type: Application
    Filed: September 11, 2008
    Publication date: March 11, 2010
    Applicant: Powership Semiconductor Corp.
    Inventor: Yi-Shiang Chang