Abstract: A method for performing data fragmentation reduction control of a memory device in a predetermined communications architecture with aid of fragmentation information detection, associated apparatus and computer-readable medium are provided.

Abstract: A method for evaluating a margin of at least one parameter utilized by a transmission interface includes: step (A) setting a value of a first parameter utilized by a host device to a first test value selected from a first group; (B) setting a value of a second parameter utilized by a data storage device to a second test value selected from a second group; (C) controlling the data storage device to perform a predetermined testing procedure to test whether the data storage device functions normally when the first test value and the second test value are applied; and (D) changing the first test value or the second test value and re-performing steps (A) to (C), wherein step (D) is repeatedly performed until all the test values in the first group and the second group have been tested.

Abstract: A heat sink comprises a first portion and a second portion. The first portion is configured to contact a heat-generating electronic component. The first portion is formed from a first group of materials and has a first plurality of fins. The second portion is coupled to the first portion. The second portion is formed from a second group of materials and has a second plurality of fins. The second group of materials is different than the first group of materials. The first group of materials can include extruded aluminum, stamped aluminum, or both. The second group of materials can include die-cast metal. The first plurality of fins can have a smaller fin pitch than the second plurality of fins. The heat sink can further comprise a third portion coupled to the first portion, such that the first portion is positioned between the second portion and the third portion.

Abstract: A dust-proof telecommunication system is disclosed. The dust-proof telecommunication system includes a chassis, critical components located within the chassis, and a filter module located within the chassis near at least some of the critical components that need to be cooled. For example, the critical components include a central processing unit (CPU), a system on chip (SoC), a memory module, a PCIe card, and/or a chipset. The filter module has a filter cover that surrounds at least in part the critical components, a first air filter located at an inlet of an airflow, and a second air filter located at an outlet. The critical components located at a protective space within the chassis receive and are cooled by the airflow passing through the air filter.

Abstract: A computing system including a water-resistant chassis, at least one electronic component with a heat sink, and a gap filler. The heat sink includes an arrangement of fins separated by inter-fin spaces. The gap filler is in contact with both the heat sink and the water-resistant chassis. The gap filler is positioned in the inter-fin spaces to provide a heat conduction path between the heat sink and the chassis.

Abstract: A link down detector and a link down detecting method for Ethernet are provided. The link down detecting method includes the following steps. Firstly, a received signal is received, and a high-frequency band signal is extracted from the received signal. Consequently, the high-frequency band signal is formed as an extraction signal. Then, a high-frequency band power value of the extraction signal is calculated, and a full band power value of the received signal is calculated. Then, a ratio value of the high-frequency band power value to the full band power value is calculated. In a link up status, if the ratio value is changed dramatically in a specified time, a link down signal is asserted to indicate that a network device connected to the Ethernet is switched to a link down status.

Abstract: A pixel circuit includes a capacitor, a light emitting control transistor, a driving transistor, and multiple light emitting transistors. The light emitting control transistor includes a gate electrode coupled to a light emitting control signal, a source electrode coupled to a supply voltage, and a drain electrode. The driving transistor includes a gate electrode coupled to the capacitor, a source electrode coupled to the drain electrode of the light emitting control transistor, and a drain electrode. Each light emitting transistor includes a gate electrode coupled to a respective light emitting signal, a source electrode coupled to the drain electrode of the driving transistor, and a drain electrode coupled to a respective light emitting element. Each light emitting signal turns on the respective light emitting transistor during a respective light emitting period within a frame period to cause the respective light emitting element to emit a light.

Abstract: A method for performing data fragmentation reduction control of a memory device in a predetermined communications architecture with aid of fragmentation information detection, associated apparatus and computer-readable medium are provided.

Abstract: A pixel circuit includes a capacitor, a light emitting control transistors, a driving transistor, and multiple light emitting transistors. The light emitting control transistor includes a gate electrode coupled to a light emitting control signal, a source electrode coupled to a supply voltage, and a drain electrode. The driving transistor includes a gate electrode coupled to the capacitor, a source electrode coupled to the drain electrode of the light emitting control transistor, and a drain electrode. Each light emitting transistor includes a gate electrode coupled to a respective light emitting signal, a source electrode coupled to the drain electrode of the driving transistor, and a drain electrode coupled to a respective light emitting element. Each light emitting signal turns on the respective light emitting transistor during a respective light emitting period within a frame period to cause the respective light emitting element to emit a light.

Abstract: The power supply device is configured on an aircraft and includes a secondary battery, a transformer, a fuel cell and a bypass switch. The transformer is electrically connected between the secondary battery and the aircraft. The fuel cell is suitable for providing a first output current to the aircraft. The bypass switch is connected in parallel with the transformer. The transformer has a first output voltage set value. When a first output terminal voltage of the fuel cell is lower than the first output voltage set value and the bypass switch is in a non-conducting state, a second output current of the secondary battery is provided to the aircraft via the transformer. When the first output terminal voltage is lower than the first output voltage set value and the bypass switch is in a conducting state, the second output current is provided to the aircraft via the bypass switch.

Abstract: A computing system including a water-resistant chassis, at least one electronic component with a heat sink, and a gap filler. The heat sink includes an arrangement of fins separated by inter-fin spaces. The gap filler is in contact with both the heat sink and the water-resistant chassis. The gap filler is positioned in the inter-fin spaces to provide a heat conduction path between the heat sink and the chassis.

Abstract: A method for evaluating a margin of at least one parameter utilized by a transmission interface includes: step (A) setting a value of a first parameter utilized by a host device to a first test value selected from a first group; (B) setting a value of a second parameter utilized by a data storage device to a second test value selected from a second group; (C) controlling the data storage device to perform a predetermined testing procedure to test whether the data storage device functions normally when the first test value and the second test value are applied; and (D) changing the first test value or the second test value and re-performing steps (A) to (C), wherein step (D) is repeatedly performed until all the test values in the first group and the second group have been tested.

Abstract: A dust-proof telecommunication system is disclosed. The dust-proof telecommunication system includes a chassis, critical components located within the chassis, and a filter module located within the chassis near at least some of the critical components that need to be cooled. For example, the critical components include a central processing unit (CPU), a system on chip (SoC), a memory module, a PCIe card, and/or a chipset. The filter module has a filter cover that surrounds at least in part the critical components, a first air filter located at an inlet of an airflow, and a second air filter located at an outlet. The critical components located at a protective space within the chassis receive and are cooled by the airflow passing through the air filter.

Abstract: A heat sink comprises a first portion and a second portion. The first portion is configured to contact a heat-generating electronic component. The first portion is formed from a first group of materials and has a first plurality of fins. The second portion is coupled to the first portion. The second portion is formed from a second group of materials and has a second plurality of fins. The second group of materials is different than the first group of materials. The first group of materials can include extruded aluminum, stamped aluminum, or both. The second group of materials can include die-cast metal. The first plurality of fins can have a smaller fin pitch than the second plurality of fins. The heat sink can further comprise a third portion coupled to the first portion, such that the first portion is positioned between the second portion and the third portion.

Abstract: The invention relates to a method, a non-transitory computer-readable storage medium, and an apparatus for executing an embedded multi-media card (eMMC) command. The method is performed by a processing unit of a flash controller to include: receiving an eMMC command from a host side; and performing a first function associated with a host performance acceleration (HPA) mode according to content of reserved bits of the eMMC command. The HPA mode allows the host side to allocate space in a system memory as an HPA buffer. The HPA buffer stores logical-block-address to physical-block-address (L2P) mapping entries obtained from the flash controller, and each L2P mapping entry stores information indicating which physical address that user data of a corresponding logical address is physically stored in a flash device, thereby enabling the host side to issue an HPA read command carrying the physical address to the flash controller.

Abstract: A demand forecasting method and a demand forecasting apparatus are provided. A preliminary prediction amount corresponding to a part number is obtained based on historical demand data. A demand probability of the part number is calculated based on the preliminary prediction amount. A prediction demand amount corresponding to the part number is obtained based on the historical demand data, the preliminary prediction amount and the demand probability.

Abstract: A control system and a control method of fuel cell stacks are provided. The control system includes a set of fuel cell stacks, a secondary battery, a monitoring device, and a control device. Each fuel cell stack has a power output that can be independently started up or shut down. The secondary battery is connected to power output terminals of the fuel cell stacks via a power transmission path. The monitoring device is configured to monitor an electrical parameter of the power transmission path. The control device receives an electrical parameter signal from the monitoring device, and outputs a control signal to shut down or start up the power output of at least one of the fuel cell stacks if the electrical parameter's value is higher than a predetermined upper limit or lower than a predetermined lower limit.

Abstract: Provided herein is a method for improving growth, stress tolerance and productivity of a plant. Also provided herein is a method for increasing seed quality of a plant. Specifically, the disclosure provides a method for improving growth, stress tolerance and productivity of a plant, comprising: providing a transgenic plant, which includes a reduced expression on an MYBS2 gene as relative to its wild-type counterpart; and a method for increasing seed quality of a plant, comprising: providing a seed from a transgenic plant, which overexpresses a full-length MYBS2 gene or a mutant MYBS2 gene as relative to its wild-type counterpart.

Abstract: The invention relates to methods, and an apparatus for data reads in a host performance acceleration (HPA) mode. One method is performed by a host side to include: issuing a switch command to a flash controller to request the flash controller to activate an HPA function, and an acquisition function for a logical-block-address to physical-block-address (L2P) mapping table; issuing a write_multiple_block command to the flash controller to transfer a data block to a flash controller, where the data block includes a region number and a sub-region number; issuing a read_multiple_block command to the flash controller to obtain a plurality of L2P mapping entries corresponding to the region number and the sub-region number from the flash controller. The host side and the flash controller communicate with each other in an embedded multi-media card (eMMC) protocol.

Abstract: The invention relates to methods, and an apparatus for data reads in a host performance acceleration (HPA) mode. One method is performed by a host side to include: searching an HPA buffer in a system memory for a logical-block-address to physical-block-address (L2P) mapping entry corresponding to a logical block address (LBA); issuing a switch command to a flash controller to request the flash controller to activate an HPA function, and does not activate an acquisition function for an L2P mapping table, where the host side and the flash controller communicate with each other in an embedded multi-media card (eMMC) protocol; issuing a write_multiple_block command to the flash controller to transfer a first data block to the flash controller, which includes the first L2P mapping entry; and issuing a read_multiple_block command to obtain data corresponding to the first L2P mapping entry from the flash controller.