Abstract: A discrete cosine transform (DCT) and inverse discrete cosine transform (IDCT) circuit includes a microcode memory, a processor, and a butterfly operation circuit. The microcode memory stores multiple microcode groups corresponding to DCT/IDCT operations and each of the microcode groups includes a series of microcodes. The processor obtains one of the microcode groups corresponding to one of the DCT/IDCT operations to be performed and retrieves microcodes in the obtained microcode group in sequence. The butterfly operation circuit performs butterfly operations according to the retrieved microcodes to execute one of the DCT/IDCT operations.

Abstract: A video decoding method includes receiving video data and transforming the video data from a Huffman tree to at least one full tree and at least one one-side tree. One microcode corresponding to the video coding standard that has encoded the received video data is read where a format of the read microcode is determined. The method further includes reading video data from the transformed video data according to the consuming length of the read microcode if the format of the read microcode is a leaf, and decoding the read video data according to the decoding field of the read microcode to output a decoding result.

Abstract: A discrete cosine transformation circuit comprising a pipeline with a memory stage and an arithmetic stage. The arithmetic stage comprises first and second arithmetic logic units (ALU). Each of the ALUs receives from the memory a set of image data, performs a first calculation on the set of image data and outputs calculation result thereof in a first clock cycle. A path in the circuit directs the result to the memory stage, such that at least one ALU can selectively receive the result from the path in a clock cycle subsequent to the first clock cycle.

Abstract: An entropy decoding method includes retrieving video data corresponding to an microcode, operating an entropy decoding operation on the video data to acquire a result, and retrieving video data corresponding to a subsequent microcode according to a MPS synchronously. The method further includes determining if the MPS matches the result, and operating an entropy decoding operation according to the subsequent microcode on the video data corresponding to the subsequent microcode if the MPS matches the result.

Abstract: A multi-standard video decoding system comprises a memory, a multi-master bridge interface, a peer-to-peer bus, a plurality of processors and a plurality of hardware accelerators. The memory stores bit stream and temporal data produced during decoding flow. The multi-master bridge interface is connected to the memory. At least one of the plurality of processors receives bit streams from the memory via the multi-master bridge interface. Each of the plurality of hardware accelerators receives instructions from one of the plurality of the processors and operates related video decoding flow, and accesses the memory via the multi-master bridge interface. The peer-to-peer bus connects the plurality of processors and the plurality of hardware accelerators.

Abstract: An entropy decoding device offers all nodes on a decoding tree, and a most probable symbol for each node, and predicts presumptive information of a next node. The entropy decoding device decodes an encoded bit stream, and output a decoded content that includes real information of the next node. The entropy decoding device further generates a flush instruction to the table look-up module, when the prediction misses, and updates the most probable symbol.

Abstract: An entropy decoding method includes retrieving video data corresponding to an microcode, operating an entropy decoding operation on the video data to acquire a result, and retrieving video data corresponding to a subsequent microcode according to a MPS synchronously. The method further includes determining if the MPS matches the result, and operating an entropy decoding operation according to the subsequent microcode on the video data corresponding to the subsequent microcode if the MPS matches the result.

Abstract: A video decoding method includes receiving video data and transforming the video data from a Huffman tree to at least one full tree and at least one one-side tree. One microcode corresponding to the video coding standard that has encoded the received video data is read where a format of the read microcode is determined. The method further includes reading video data from the transformed video data according to the consuming length of the read microcode if the format of the read microcode is a leaf, and decoding the read video data according to the decoding field of the read microcode to output a decoding result.

Abstract: An entropy decoding device offers all nodes on a decoding tree, and a most probable symbol for each node, and predicts presumptive information of a next node. The entropy decoding device decodes an encoded bit stream, and output a decoded content that includes real information of the next node. The entropy decoding device further generates a flush instruction to the table look-up module, when the prediction misses, and updates the most probable symbol.

Abstract: A video codec device to perform interpolations on a reference frame is provided. The video codec device comprises a full pixel register, an interpolation filter array, a half pixel register and a result register. The interpolation filter array performs half interpolations to generate half pixels of the reference frame to the half pixel register. The half pixels stored in the half pixel register are variable for quarter interpolations. When all the half interpolations of the reference frames are finished, the interpolation filter array performs the quarter interpolations utilizing the generated half pixels, and generates quarter pixels of the reference frames to the result register.

Abstract: A discrete cosine transform (DCT) and inverse discrete cosine transform (IDCT) circuit includes a microcode memory, a processor, and a butterfly operation circuit. The microcode memory stores multiple microcode groups corresponding to DCT/IDCT operations and each of the microcode groups includes a series of microcodes. The processor obtains one of the microcode groups corresponding to one of the DCT/IDCT operations to be performed and retrieves microcodes in the obtained microcode group in sequence. The butterfly operation circuit performs butterfly operations according to the retrieved microcodes to execute one of the DCT/IDCT operations.

Abstract: A discrete cosine transformation circuit comprising a pipeline with a memory stage and an arithmetic stage. The arithmetic stage comprises first and second arithmetic logic units (ALU). Each of the ALUs receives from the memory a set of image data, performs a first calculation on the set of image data and outputs calculation result thereof in a first clock cycle. A path in the circuit directs the result to the memory stage, such that at least one ALU can selectively receive the result from the path in a clock cycle subsequent to the first clock cycle.

Abstract: A signal relay device for accessing an external memory is provided. The signal relay device includes a bus arbiter and a burst access engine. The bus arbiter performs bus arbitration among main masters on a bus. The burst access engine exchanges signals with the bus arbiter and an external memory controller. The signal relay device facilitates data transfer of large groups of read/write commands between the main masters and the external memory controller.

Abstract: A signal relay device for accessing an external memory is provided. The signal relay device includes a bus arbiter and a burst access engine. The bus arbiter performs bus arbitration among main masters on a bus. The burst access engine exchanges signals with the bus arbiter and an external memory controller. The signal relay device facilitates data transfer of large groups of read/write commands between the main masters and the external memory controller.