Patents by Inventor Yi-Shing Chang

Yi-Shing Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190306468
    Abstract: A wireless monitoring system includes a wireless monitor using a battery as a power source, a transceiver for receiving an image photographed by the wireless monitor from a remote end, and an image identification unit installed in a cloud server. After a sensor of the wireless monitor is triggered, the photography module starts shooting, and the transceiver transmits the image to the cloud server for identification. If the photographed image is not a target to be monitored, the transceiver will drive the photography module of the wireless monitor to stop shooting, so as to extend the power endurance of the wireless monitor effectively.
    Type: Application
    Filed: April 2, 2018
    Publication date: October 3, 2019
    Applicant: Mars Semiconductor Corp.
    Inventors: Tsung-Ming HO, Yi-Shing CHANG
  • Publication number: 20190306807
    Abstract: A wireless transmission system capable of automatically adjusting transmission power includes a main wireless apparatus and plural secondary wireless apparatuses, and the main wireless apparatus is capable of detecting the data rate between the secondary wireless apparatuses, and increasing or decreasing the transmission power of any one of the secondary wireless apparatuses by a master controller, or increasing or decreasing the transmission power of the main wireless apparatus, so that the data rate and/or transmitting distance between the main wireless apparatus and the secondary wireless apparatuses can be optimized.
    Type: Application
    Filed: April 2, 2018
    Publication date: October 3, 2019
    Applicant: Mars Semiconductor Corp.
    Inventors: Tsung-Ming HO, Yi-Shing CHANG
  • Patent number: 10433263
    Abstract: A wireless transmission system capable of automatically adjusting transmission power includes a main wireless apparatus and plural secondary wireless apparatuses, and the main wireless apparatus is capable of detecting the data rate between the secondary wireless apparatuses, and increasing or decreasing the transmission power of any one of the secondary wireless apparatuses by a master controller, or increasing or decreasing the transmission power of the main wireless apparatus, so that the data rate and/or transmitting distance between the main wireless apparatus and the secondary wireless apparatuses can be optimized.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: October 1, 2019
    Assignee: Mars Semiconductor Corp
    Inventors: Tsung-Ming Ho, Yi-Shing Chang
  • Patent number: 7385244
    Abstract: A method for forming an improved etching hardmask oxide layer in a polysilicon etching process including providing a planarized semiconductor wafer process surface including adjacent first exposed polysilicon portions and exposed oxide portions; selectively etching through a thickness portion of the exposed oxide portions; thermally growing an oxide hardmask layer over the exposed polysilicon portions to form oxide hardmask portions; exposing second exposed polysilicon portions adjacent at least one oxide hardmask portion; and, etching through a thickness portion of the second exposed polysilicon portions.
    Type: Grant
    Filed: February 3, 2005
    Date of Patent: June 10, 2008
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Shing Chang, Yeur-Luen Tu, Chia-Shiung Tsai, Wen-Ting Chu
  • Publication number: 20080076243
    Abstract: A non-volatile memory is described. A substrate comprising a stacked layer is provided. A sacrificial layer is deposited and patterned to form a first opening. A first spacer is formed on sidewalls of the first opening, and the stacked layer is etched using the first spacer as a first mask to form a second opening. An isolation layer is formed in a portion of the first and the second openings, and a conductive filling layer is formed thereon. The stacked layer is etched using a portion of the conductive filling layer as a second mask.
    Type: Application
    Filed: November 21, 2007
    Publication date: March 27, 2008
    Inventor: Yi-Shing Chang
  • Patent number: 7227218
    Abstract: A memory device and the method for manufacturing same is disclosed. The device comprises a first oxide layer on top of a substrate, a floating gate layer on top of the first oxide layer, a second oxide layer over the floating gate layer, wherein the second oxide layer and the floating gate layer have a first opening and a second opening respectively, and wherein the width of second opening is bigger than the width of the narrowest region of the first opening so that the floating gate layer is pulled back horizontally underneath the second oxide layer. A source region is in the substrate underneath the first oxide layer, and a third oxide layer fills in the first and second openings conforming to the contour thereof, wherein the third oxide has a third opening to reach a portion of the source region. Further, a control gate material fills in the third opening.
    Type: Grant
    Filed: March 30, 2005
    Date of Patent: June 5, 2007
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Shing Chang, Wen-Ting Chu
  • Patent number: 7067891
    Abstract: Each of an elevated diode sensor optoelectronic product and a method for fabricating the elevated diode sensor optoelectronic product employs a sidewall passivation dielectric layer passivating a sidewall of a patterned conductor layer which serves as a bottom electrode for an elevated diode within the elevated diode sensor optoelectronic product. The sidewall passivation dielectric layer eliminates contact between the patterned conductor layer and an intrinsic diode material layer within the elevated diode, thus providing enhanced performance of the elevated diode sensor optoelectronic product.
    Type: Grant
    Filed: November 4, 2003
    Date of Patent: June 27, 2006
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Dunn-Nian Yaung, Shou-Gwo Wuu, Ho-Ching Chien, Yi-Shing Chang
  • Patent number: 7030444
    Abstract: A split gate flash memory cell structure is disclosed for prevention of reverse tunneling. A gate insulator layer is formed over a semiconductor surface and a floating gate is disposed over the gate insulator layer. A floating gate insulator layer is disposed over the floating gate and sidewall insulator spacers are disposed along bottom portions of the floating gate sidewall adjacent to said gate insulator layer. The sidewall insulator spacers are formed from a spacer insulator layer that had been deposited in a manner that constitutes a minimal expenditure of an available thermal budget and etching processes used in fashioning the sidewall insulator spacers etch the spacer insulator layer faster than the gate insulator layer and the floating gate insulator layer. An intergate insulator layer is disposed over exposed portions of the gate insulator layer, the floating gate, the floating gate insulator layer and the sidewall insulator spacers.
    Type: Grant
    Filed: February 25, 2004
    Date of Patent: April 18, 2006
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Chi Tu, Wen-Ting Chu, Yi-Shing Chang, Yi-Jiun Lin
  • Publication number: 20060068546
    Abstract: A non-volatile memory is described. A substrate comprising a stacked layer is provided. A sacrificial layer is deposited and patterned to form a first opening. A first spacer is formed on sidewalls of the first opening, and the stacked layer is etched using the first spacer as a first mask to form a second opening. An isolation layer is formed in a portion of the first and the second openings, and a conductive filling layer is formed thereon. The stacked layer is etched using a portion of the conductive filling layer as a second mask.
    Type: Application
    Filed: September 29, 2004
    Publication date: March 30, 2006
    Inventor: Yi-Shing Chang
  • Publication number: 20050184331
    Abstract: A split gate flash memory cell structure is disclosed for prevention of reverse tunneling. A gate insulator layer is formed over a semiconductor surface and a floating gate is disposed over the gate insulator layer. A floating gate insulator layer is disposed over the floating gate and sidewall insulator spacers are disposed along bottom portions of the floating gate sidewall adjacent to said gate insulator layer. The sidewall insulator spacers are formed from a spacer insulator layer that had been deposited in a manner that constitutes a minimal expenditure of an available thermal budget and etching processes used in fashioning the sidewall insulator spacers etch the spacer insulator layer faster than the gate insulator layer and the floating gate insulator layer. An intergate insulator layer is disposed over exposed portions of the gate insulator layer, the floating gate, the floating gate insulator layer and the sidewall insulator spacers.
    Type: Application
    Filed: February 25, 2004
    Publication date: August 25, 2005
    Inventors: Kuo-Chi Tu, Wen-Ting Chu, Yi-Shing Chang, Yi-Jiun Lin
  • Publication number: 20050179080
    Abstract: A memory device and the method for manufacturing same is disclosed. The device comprises a first oxide layer on top of a substrate, a floating gate layer on top of the first oxide layer, a second oxide layer over the floating gate layer, wherein the second oxide layer and the floating gate layer have a first opening and a second opening respectively, and wherein the width of second opening is bigger than the width of the narrowest region of the first opening so that the floating gate layer is pulled back horizontally underneath the second oxide layer. A source region is in the substrate underneath the first oxide layer, and a third oxide layer fills in the first and second openings conforming to the contour thereof, wherein the third oxide has a third opening to reach a portion of the source region. Further, a control gate material fills in the third opening.
    Type: Application
    Filed: March 30, 2005
    Publication date: August 18, 2005
    Inventors: Yi-Shing Chang, Wen-Ting Chu
  • Publication number: 20050133850
    Abstract: A method for forming an improved etching hardmask oxide layer in a polysilicon etching process including providing a planarized semiconductor wafer process surface including adjacent first exposed polysilicon portions and exposed oxide portions; selectively etching through a thickness portion of the exposed oxide portions; thermally growing an oxide hardmask layer over the exposed polysilicon portions to form oxide hardmask portions; exposing second exposed polysilicon portions adjacent at least one oxide hardmask portion; and, etching through a thickness portion of the second exposed polysilicon portions.
    Type: Application
    Filed: February 3, 2005
    Publication date: June 23, 2005
    Inventors: Yi-Shing Chang, Yeur-Luen Tu, Chia-Shiung Tsai, Wen-Ting Chu
  • Patent number: 6890821
    Abstract: A memory device and the method for manufacturing the same is disclosed. The device includes a first oxide layer on top of a substrate, a floating gate layer on top of the first oxide layer, and a second oxide layer over the floating gate layer. The second oxide layer and the floating gate layer have a first opening and a second opening respectively wherein the width of second opening is bigger than the width of the narrowest region of the first opening so that the floating gate layer is pulled back horizontally underneath the second oxide layer. A source region is in the substrate underneath the first oxide layer, and a third oxide layer fills in the first and second openings conforming to the contour thereof. The third oxide has a third opening to reach a portion of the source region. Further, a control gate material fills in the third opening.
    Type: Grant
    Filed: July 11, 2003
    Date of Patent: May 10, 2005
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Shing Chang, Wen-Ting Chu
  • Publication number: 20050093086
    Abstract: Each of an elevated diode sensor optoelectronic product and a method for fabricating the elevated diode sensor optoelectronic product employs a sidewall passivation dielectric layer passivating a sidewall of a patterned conductor layer which serves as a bottom electrode for an elevated diode within the elevated diode sensor optoelectronic product. The sidewall passivation dielectric layer eliminates contact between the patterned conductor layer and an intrinsic diode material layer within the elevated diode, thus providing enhanced performance of the elevated diode sensor optoelectronic product.
    Type: Application
    Filed: November 4, 2003
    Publication date: May 5, 2005
    Inventors: Dunn-Nian Yaung, Shou-Gwo Wuu, Ho-Ching Chien, Yi-Shing Chang
  • Patent number: 6855602
    Abstract: A method for forming an improved etching hardmask oxide layer in a polysilicon etching process including providing a planarized semiconductor wafer process surface including adjacent first exposed polysilicon portions and exposed oxide portions; selectively etching through a thickness portion of the exposed oxide portions; thermally growing an oxide hardmask layer over the exposed polysilicon portions to form oxide hardmask portions; exposing second exposed polysilicon portions adjacent at least one oxide hardmask portion; and, etching through a thickness portion of the second exposed polysilicon portions.
    Type: Grant
    Filed: March 27, 2003
    Date of Patent: February 15, 2005
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Shing Chang, Yeur-Luen Tu, Chia-Shiung Tsai, Wen-Ting Chu
  • Publication number: 20050009273
    Abstract: A memory device and the method for manufacturing the same is disclosed. The device includes a first oxide layer on top of a substrate, a floating gate layer on top of the first oxide layer, and a second oxide layer over the floating gate layer. The second oxide layer and the floating gate layer have a first opening and a second opening respectively wherein the width of second opening is bigger than the width of the narrowest region of the first opening so that the floating gate layer is pulled back horizontally underneath the second oxide layer. A source region is in the substrate underneath the first oxide layer, and a third oxide layer fills in the first and second openings conforming to the contour thereof. The third oxide has a third opening to reach a portion of the source region. Further, a control gate material fills in the third opening.
    Type: Application
    Filed: July 11, 2003
    Publication date: January 13, 2005
    Inventors: Yi-Shing Chang, Wen-Ting Chu
  • Publication number: 20040188749
    Abstract: A method for forming an improved etching hardmask oxide layer in a polysilicon etching process including providing a planarized semiconductor wafer process surface including adjacent first exposed polysilicon portions and exposed oxide portions; selectively etching through a thickness portion of the exposed oxide portions; thermally growing an oxide hardmask layer over the exposed polysilicon portions to form oxide hardmask portions; exposing second exposed polysilicon portions adjacent at least one oxide hardmask portion; and, etching through a thickness portion of the second exposed polysilicon portions.
    Type: Application
    Filed: March 27, 2003
    Publication date: September 30, 2004
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Shing Chang, Yeur-Luen Tu, Chia-Shiung Tsai, Wen-Ting Chu