Abstract: A differential amplification device and a compensation method thereof. The differential amplification device includes a first terminal signal circuit, a second terminal signal circuit and a controller. The first terminal signal circuit and the second terminal signal circuit respectively generate a first terminal signal and a second terminal signal of a differential output signal to a first terminal of a transmission path. The controller adjusts first element parameters of the first terminal signal circuit or second element parameters of the second terminal signal circuit based on a transmitted differential signal at a second terminal of the transmission path to compensate for asymmetric influence by the transmission path on the first terminal signal and the second terminal signal of the transmitted differential signal. Adjustment of the first element parameter of the first terminal signal circuit is independent of adjustment of the second element parameter of the second terminal signal circuit.

Abstract: A protection circuit applied in a hub chip including a power pin, a first data pin, and a second data pin is provided. A voltage generation circuit generates and adjusts output voltage according to the voltage of the power pin and the voltage of the first data pin. A PMOS transistor includes a first gate, a first electrode, a second electrode, and a first bulk. The first electrode is coupled to the power pin. The second electrode is coupled to the first data pin. The first bulk receives the output voltage. A detection circuit is coupled to the first gate and detects the voltage of the power pin. In response to the voltage of the power pin being equal to the first voltage, the detection circuit transmits the voltage of the first data pin to the first gate.

Abstract: A connection interface conversion chip, a connection interface conversion device and an operation method are provided. The connection interface conversion chip includes a USB interface circuit, a DP interface circuit, a USB core circuit and a switching circuit. The USB interface circuit is suitable for coupling to a USB connector. The DP interface circuit is coupled to a DP sink device through a DP connector. The USB core circuit is coupled to both the USB interface circuit and the DP interface circuit. The switching circuit is coupled to both the USB interface circuit and the DP interface circuit. The switching circuit supports only one specific conduction mode that only allows transmitting DP signals between the USB interface circuit and the DP interface circuit.

Abstract: A protection circuit applied in a hub chip including a power pin, a first data pin, and a second data pin is provided. A voltage generation circuit generates and adjusts output voltage according to the voltage of the power pin and the voltage of the first data pin. A PMOS transistor includes a first gate, a first electrode, a second electrode, and a first bulk. The first electrode is coupled to the power pin. The second electrode is coupled to the first data pin. The first bulk receives the output voltage. A detection circuit is coupled to the first gate and detects the voltage of the power pin. In response to the voltage of the power pin being equal to the first voltage, the detection circuit transmits the voltage of the first data pin to the first gate.

Abstract: A connection interface conversion chip, a connection interface conversion device and an operation method are provided. The connection interface conversion chip includes a USB interface circuit, a DP interface circuit, a USB core circuit and a switching circuit. The USB interface circuit is suitable for coupling to a USB connector. The DP interface circuit is coupled to a DP sink device through a DP connector. The USB core circuit is coupled to both the USB interface circuit and the DP interface circuit. The switching circuit is coupled to both the USB interface circuit and the DP interface circuit. The switching circuit supports only one specific conduction mode that only allows transmitting DP signals between the USB interface circuit and the DP interface circuit.

Abstract: A connection interface conversion chip, a connection interface conversion device and an operation method are provided. The connection interface conversion chip includes a USB interface circuit, a DP interface circuit, a USB core circuit and a switching circuit. The USB interface circuit is suitable for coupling to a USB connector. The DP interface circuit is suitable for coupling to a DP connector. In a first operation mode, at least one USB signal pair received by the USB connector is transmitted to the USB core circuit through the USB interface circuit. The USB core circuit decodes the USB signal pair and generates DP data. The DP data is transmitted to the DP connector by the DP interface circuit. In a second operation mode, the DP data received by the USB connector is transmitted to the DP connector through the USB interface circuit, the switching circuit and the DP interface circuit.

Abstract: A connection interface conversion chip, a connection interface conversion device and an operation method are provided. The connection interface conversion chip includes a USB interface circuit, a DP interface circuit, a USB core circuit and a switching circuit. The USB interface circuit is suitable for coupling to a USB connector. The DP interface circuit is suitable for coupling to a DP connector. In a first operation mode, at least one USB signal pair received by the USB connector is transmitted to the USB core circuit through the USB interface circuit. The USB core circuit decodes the USB signal pair and generates DP data. The DP data is transmitted to the DP connector by the DP interface circuit. In a second operation mode, the DP data received by the USB connector is transmitted to the DP connector through the USB interface circuit, the switching circuit and the DP interface circuit.

Abstract: A universal serial bus circuit including a power circuit and a terminating circuit is provided. The power circuit provides a differential signal. The terminating circuit is coupled to the power circuit. The terminating circuit receives the differential signal through the first signal output terminal and the second signal output terminal, and the terminating circuit includes a first load circuit and a second load circuit. When the universal serial bus circuit is operated in a handshake mode, the terminating circuit receives the differential signal through the first load circuit and the second load circuit, and outputs a pulse signal through the first signal output terminal and the second signal output terminal. When the universal serial bus circuit is operated in a normal mode, the terminating circuit receives the differential signal through the first load circuit, and outputs a data signal through the first signal output terminal and the second signal output terminal.

Abstract: A battery management system for a battery pack including a plurality of battery cells connected in series is provided. The battery management system includes a first switching unit coupled to an anode of a first battery cell of the battery pack, having a first P-type transistor coupled to the anode of the first battery cell, a first resistor coupled between the anode of the first battery cell and a gate of the first P-type transistor, and a current mirror coupled to the gate of the first P-type transistor and the first resistor, draining a first mirror current from the first resistor in response to a control signal, so as to turn on the first P-type transistor. The system further includes a detection circuit coupled to the first switching unit.

Abstract: A battery management system for a battery pack including a plurality of battery cells connected in series is provided. The battery management system includes a first switching unit coupled to an anode of a first battery cell of the battery pack, having a first P-type transistor coupled to the anode of the first battery cell, a first resistor coupled between the anode of the first battery cell and a gate of the first P-type transistor, and a current mirror coupled to the gate of the first P-type transistor and the first resistor, draining a first mirror current from the first resistor in response to a control signal, so as to turn on the first P-type transistor. The system further includes a detection circuit coupled to the first switching unit.

Abstract: A battery management system for a battery pack including a plurality of battery cells connected in series is provided. The battery management system includes a voltage divider, a plurality of switching units and a detection circuit. Each switching unit is corresponding to one of the battery cell and coupled between an anode of the corresponding battery cell and the voltage divider. When a control signal directs one of the switching units to turn on, the voltage divider divides a voltage difference transmitted from the one of the switching units to obtain a divided voltage signal, and transmits the divided voltage signal to the detection circuit, and the detection circuit detects the voltage difference according to the divided voltage signal, wherein the voltage difference is a voltage difference between an anode of the battery cell corresponding to the one of the switching units and a ground.

Abstract: A battery management system for a battery pack including a plurality of battery cells connected in series is provided. The battery management system includes a voltage divider, a plurality of switching units and a detection circuit. Each switching unit is corresponding to one of the battery cell and coupled between an anode of the corresponding battery cell and the voltage divider. When a control signal directs one of the switching units to turn on, the voltage divider divides a voltage difference transmitted from the one of the switching units to obtain a divided voltage signal, and transmits the divided voltage signal to the detection circuit, and the detection circuit detects the voltage difference according to the divided voltage signal, wherein the voltage difference is a voltage difference between an anode of the battery cell corresponding to the one of the switching units and a ground.