Abstract: A testing method of electronic devices, each of which includes a central processing unit (CPU) for running an operating system (OS), includes the following steps when testing one of the electronic devices. The specification of the CPU of the electronic device and the version of the OS run on the CPU are identified. A test script of the electronic device is searched from a script lookup table according to the specification of the CPU and the version of the OS. The script lookup table records a variety of test scripts related to the specification of a variety of CPUs of a variety of electronic devices in combination with the version of a variety of operating systems. The found test script is provided to a testing module. The electronic device is tested by the testing module according to the found test script.

Abstract: A process of forming a lateral PNP transistor includes the steps of: providing a chip of semiconductor material including an isolated N- device region; implanting N dopant material at a relatively low power and low dosage into a selected implant region of the device region; implanting N dopant material at a relatively higher power and higher dosage into the implant region; and forming emitter and collector regions in the device region such that an intrinsic base region is defined between the collector and emitter regions in the implant region.

Abstract: A process of forming a lateral PNP transistor includes the steps of: providing a chip of semiconductor material including an isolated N- device region; implanting N dopant material at a relatively low power and low dosage into a selected implant region of the device region; implanting N dopant material at a relatively higher power and higher dosage into the implant region; and forming emitter and collector regions in the device region such that an intrinsic base region is defined between the collector and emitter regions in the implant region.

Abstract: A method for making a lateral PNP transistor simultaneously with an NPN transistor and the resultant device wherein a first mask defines a base-width by the resistor implant for a P-type resistor and a second mask is overlaid asymmetrically on said first mask to partially cover the collector. At the same time that the NPN extrinsic base contact is made, P-type dopants are introduced in the areas exposed by the first and second masks to provide an emitter and a collector contact for the PNP transistor.