Patents by Inventor Yi-Shun Huang
Yi-Shun Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240096998Abstract: The present disclosure describes a method for forming metallization layers that include a ruthenium metal liner and a cobalt metal fill. The method includes depositing a first dielectric on a substrate having a gate structure and source/drain (S/D) structures, forming an opening in the first dielectric to expose the S/D structures, and depositing a ruthenium metal on bottom and sidewall surfaces of the opening. The method further includes depositing a cobalt metal on the ruthenium metal to fill the opening, reflowing the cobalt metal, and planarizing the cobalt and ruthenium metals to form S/D conductive structures with a top surface coplanar with a top surface of the first dielectric.Type: ApplicationFiled: November 21, 2023Publication date: March 21, 2024Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shuen-Shin LIANG, Chij-chien CHI, Yi-Ying LIU, Chia-Hung CHU, Hsu-Kai CHANG, Cheng-Wei CHANG, Chein-Shun LIAO, Keng-chu LIN, KAi-Ting HUANG
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Publication number: 20190065648Abstract: A method for establishing an aging model of a device is provided. The device is measured to obtain degradation information of the device under an operating condition, wherein the device is a physical device. The degradation information is partitioned into a permanent degradation portion and an impermanent degradation portion. The impermanent degradation portion is differentiated by time to obtain a differential value. The aging model is obtained according to the differential value. When the differential value is greater than zero, a degradation of the device increases over time, and when the differential value is less than zero, the degradation of the device decreases over time.Type: ApplicationFiled: August 22, 2017Publication date: February 28, 2019Inventors: Yi-Shun HUANG, Wai-Kit LEE, Ya-Chin LIANG, Cheng HSIAO, Juan-Yi CHEN, Li-Chung HSU, Ting-Sheng HUANG, Ke-Wei SU, Chung-Kai LIN, Min-Chie JENG
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Patent number: 10216879Abstract: A method for establishing an aging model of a device is provided. The device is measured to obtain degradation information of the device under an operating condition, wherein the device is a physical device. The degradation information is partitioned into a permanent degradation portion and an impermanent degradation portion. The impermanent degradation portion is differentiated by time to obtain a differential value. The aging model is obtained according to the differential value. When the differential value is greater than zero, a degradation of the device increases over time, and when the differential value is less than zero, the degradation of the device decreases over time.Type: GrantFiled: August 22, 2017Date of Patent: February 26, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Shun Huang, Wai-Kit Lee, Ya-Chin Liang, Cheng Hsiao, Juan-Yi Chen, Li-Chung Hsu, Ting-Sheng Huang, Ke-Wei Su, Chung-Kai Lin, Min-Chie Jeng
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Patent number: 10113593Abstract: An encoder with oil gas prevention structure including a base, a shaft, a bearing, a cover and an encoding device is provided. The base includes a body and a through hole configured on the body. The shaft is disposed within the though hole. The bearing holds the shaft and is disposed within the through hole, and includes an inner ring and an outer ring wherein the inner ring is set against the first section, and the outer ring is set against a circumference of the through hole. The cover holds the shaft and adjacent to the bearing. The encoding device holds the shaft and is disposed on the cover, and includes a code disc rotatably disposed on the shaft wherein the cover is located between the bearing and the code disc. Therefore, the code disc is prevented from being contaminated by the leaking oil gas from the bearing.Type: GrantFiled: August 5, 2017Date of Patent: October 30, 2018Assignee: HIWIN MIKROSYSTEM CORP.Inventors: Wei-Kai Tseng, Jheng-Ying Lin, Yi-Shun Huang, Hsin-Wei Tsai
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Patent number: 10019545Abstract: A method includes receiving input information related to devices of an integrated circuit. A first simulation of the integrated circuit is performed over a first time period. Average temperature changes of the devices over the first time period are calculated. A second simulation of the integrated circuit is performed over a second time period using the average temperature changes of the devices. The first simulation and the second simulation are executed by a processor unit.Type: GrantFiled: June 13, 2014Date of Patent: July 10, 2018Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Min-Chie Jeng, Chung-Kai Lin, Ke-Wei Su, Yi-Shun Huang, Ya-Chin Liang, Cheng Hsiao, Juan Yi Chen, Wai-Kit Lee
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Patent number: 9829351Abstract: An encoding device includes a sensing unit having a signal transmitting element and a signal receiving element. The signal transmitting element and the signal receiving element are respectively disposed on different carrier members. Accordingly, when performing the rectification and alignment processes between the signal receiving element and the signal unit, the other components are prevented from hindering the rectification and alignment processes, whereby the rectification and alignment processes can be easily performed.Type: GrantFiled: January 29, 2016Date of Patent: November 28, 2017Assignee: HIWIN MIKROSYSTEM CORP.Inventors: Yan-Shiang Wang, Yi-Shun Huang
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Publication number: 20170219387Abstract: An encoding device includes a sensing unit having a signal transmitting element and a signal receiving element. The signal transmitting element and the signal receiving element are respectively disposed on different carrier members. Accordingly, when performing the rectification and alignment processes between the signal receiving element and the signal unit, the other components are prevented from hindering the rectification and alignment processes, whereby the rectification and alignment processes can be easily performed.Type: ApplicationFiled: January 29, 2016Publication date: August 3, 2017Inventors: Yan-Shiang WANG, Yi-Shun HUANG
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Publication number: 20150363526Abstract: A method includes receiving input information related to devices of an integrated circuit. A first simulation of the integrated circuit is performed over a first time period. Average temperature changes of the devices over the first time period are calculated. A second simulation of the integrated circuit is performed over a second time period using the average temperature changes of the devices. The first simulation and the second simulation are executed by a processor unit.Type: ApplicationFiled: June 13, 2014Publication date: December 17, 2015Inventors: Min-Chie Jeng, Chung-Kai Lin, Ke-Wei Su, Yi-Shun Huang, Ya-Chin Liang, Cheng Hsiao, Juan Yi Chen, Wai-Kit Lee
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Patent number: 9141735Abstract: The present disclosure provides systems for predicting semiconductor reliability. In an embodiment a method for predicting the semiconductor reliability includes receiving a degradation parameter input of a semiconductor device and using a degradation equation to determine a plurality of bias dependent slope values for degradation over a short time period according to the degradation parameter input. The plurality of slope values include at least two different slope values for degradation over time. The system accumulates the plurality of slope values and projects the accumulated slope values over a long time period to determine a stress effect for the semiconductor device.Type: GrantFiled: June 18, 2010Date of Patent: September 22, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jia-Lin Lo, Ke-Wei Su, Min-Chie Jeng, Feng-Ling Hsiao, Cheng Hsiao, Yi-Shun Huang, Yi-Chun Chen
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Patent number: 8370774Abstract: A method includes determining a mapping between model parameters and electrical parameters of integrated circuits. The model parameters are configured to be used by a simulation tool. A set of electrical parameters is provided, and the mapping is used to map the set of electrical parameters to a set of model parameters.Type: GrantFiled: August 30, 2010Date of Patent: February 5, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Ming Tsai, Ke-Wei Su, Cheng Hsiao, Min-Chie Jeng, Jia-Lin Lo, Feng-Ling Hsiao, Yi-Shun Huang
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Publication number: 20120054709Abstract: A method includes determining a mapping between model parameters and electrical parameters of integrated circuits. The model parameters are configured to be used by a simulation tool. A set of electrical parameters is provided, and the mapping is used to map the set of electrical parameters to a set of model parameters.Type: ApplicationFiled: August 30, 2010Publication date: March 1, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Ming Tsai, Ke-Wei Su, Cheng Hsiao, Min-Chie Jeng, Jia-Lin Lo, Feng-Ling Hsiao, Yi-Shun Huang
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Publication number: 20110313735Abstract: The present disclosure provides systems for predicting semiconductor reliability. In an embodiment a method for predicting the semiconductor reliability includes receiving a degradation parameter input of a semiconductor device and using a degradation equation to determine a plurality of bias dependent slope values for degradation over a short time period according to the degradation parameter input. The plurality of slope values include at least two different slope values for degradation over time. The system accumulates the plurality of slope values and projects the accumulated slope values over a long time period to determine a stress effect for the semiconductor device.Type: ApplicationFiled: June 18, 2010Publication date: December 22, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd. ("TSMC")Inventors: Jia-Lin Lo, Ke-Wei Su, Min-Chie Jeng, Feng-Ling Hsiao, Cheng Hsiao, Yi-Shun Huang, Yi-Chun Chen
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Publication number: 20080277257Abstract: A low-noise cost-effective keyboard includes keys arranged in rows and columns in a housing. Each key has a mounting member affixed to the housing, at least one button, at least one connecting member integrally connected between the mounting member and the at least one button in a manner that a top surface of the at least one button is higher in elevation than the top surface of the mounting member, and at least one stop flange protruding from a side of the button opposite to the connecting member in a manner that an end edge of the at least one stop flange is lower in elevation than a bottom surface of the button and the stop flange of one key suspends beneath one button of another key.Type: ApplicationFiled: September 5, 2007Publication date: November 13, 2008Applicant: Universal Scientific Industrial Co., LTD.Inventors: Chia-Ching HUANG, Yi-Shun Huang