Patents by Inventor Yi-Syuan Siao

Yi-Syuan Siao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12199156
    Abstract: A method includes forming a source/drain region, forming a dielectric layer over the source/drain region, and etching the dielectric layer to form a contact opening. The source/drain region is exposed to the contact opening. The method further includes depositing a dielectric spacer layer extending into the contact opening, etching the dielectric spacer layer to form a contact spacer in the contact opening, implanting a dopant into the source/drain region through the contact opening after the dielectric spacer layer is deposited, and forming a contact plug to fill the contact opening.
    Type: Grant
    Filed: February 8, 2022
    Date of Patent: January 14, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Meng-Han Chou, Yi-Syuan Siao, Su-Hao Liu, Huicheng Chang, Yee-Chia Yeo
  • Publication number: 20240413155
    Abstract: A method includes forming a fin structure including a first channel layer, a sacrificial layer, and a second channel layer over a substrate; forming a dummy gate structure across the fin structure; recessing the fin structure; epitaxially growing first source/drain epitaxial structures on opposite sides of the first channel layer; forming first dielectric layers to cover the first source/drain epitaxial structures, respectively; epitaxially growing second source/drain epitaxial structures on opposite sides of the second channel layer; removing the dummy gate structure and the sacrificial layer to form a gate trench between the first source/drain epitaxial structures and between the second source/drain epitaxial structures; and forming a metal gate structure in the gate trench. The second source/drain epitaxial structures are over the first dielectric layers, respectively.
    Type: Application
    Filed: June 6, 2023
    Publication date: December 12, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Yu LIN, Tien-Shun CHANG, Yi-Syuan SIAO, Su-Hao LIU, Chi On CHUI
  • Publication number: 20240387669
    Abstract: A method for fabricating an integrated circuit device includes forming first epitaxial stack comprising a first sacrificial layer and a first channel layer over a substrate; forming a second epitaxial stack comprising a second sacrificial layer and a second channel layer over the first epitaxial stack; etching a recess in the first and second epitaxial stacks, wherein the recess exposes end surfaces of the first and second channel layers; performing a first ion implantation process to form a first lightly doped region; performing a second ion implantation process to form a second lightly doped region, wherein a tilt angle of the second ion implantation process is greater than a tilt angle of the first ion implantation process; forming first and second source/drain epitaxial features in the recess; and replacing the first and the second sacrificial layers with a high-k/metal gate structure.
    Type: Application
    Filed: May 15, 2023
    Publication date: November 21, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Syuan SIAO, Chien-Yu LIN, Meng-Han CHOU, Su-Hao LIU, Chi On CHUI
  • Publication number: 20240258387
    Abstract: In an embodiment, a device includes: a first semiconductor nanostructure; a second semiconductor nanostructure adjacent the first semiconductor nanostructure; a first source/drain region on a first sidewall of the first semiconductor nanostructure; a second source/drain region on a second sidewall of the second semiconductor nanostructure, the second source/drain region completely separated from the first source/drain region; and a source/drain contact between the first source/drain region and the second source/drain region.
    Type: Application
    Filed: May 9, 2023
    Publication date: August 1, 2024
    Inventors: Yi-Syuan Siao, Meng-Han Chou, Chien-Yu Lin, Wei-Ting Chang, Tien-Shun Chang, Chin-I Kuan, Su-Hao Liu, Chi On Chui
  • Publication number: 20230261069
    Abstract: In an embodiment, a device includes: a source/drain region adjacent a channel region; an inter-layer dielectric on the source/drain region; a source/drain contact extending through the inter-layer dielectric and into the source/drain region; a metal-semiconductor alloy region between the source/drain contact and the source/drain region, the metal-semiconductor alloy region disposed beneath a top surface of the channel region, the metal-semiconductor alloy region including a first dopant; and a contact spacer around the source/drain contact, the contact spacer including the first dopant and an amorphizing impurity.
    Type: Application
    Filed: May 13, 2022
    Publication date: August 17, 2023
    Inventors: Meng-Han Chou, Yi-Syuan Siao, Su-Hao Liu, Huicheng Chang, Yee-Chia Yeo
  • Publication number: 20230034803
    Abstract: A method includes forming a source/drain region, forming a dielectric layer over the source/drain region, and etching the dielectric layer to form a contact opening. The source/drain region is exposed to the contact opening. The method further includes depositing a dielectric spacer layer extending into the contact opening, etching the dielectric spacer layer to form a contact spacer in the contact opening, implanting a dopant into the source/drain region through the contact opening after the dielectric spacer layer is deposited, and forming a contact plug to fill the contact opening.
    Type: Application
    Filed: February 8, 2022
    Publication date: February 2, 2023
    Inventors: Meng-Han Chou, Yi-Syuan Siao, Su-Hao Liu, Huicheng Chang, Yee-Chia Yeo