Abstract: A printed circuit board comprising a differential microstrip pair including a neck-down area and an ultraviolet glue coating a portion of the neck-down area of the differential microstrip pair to control an impedance of the differential microstrip pair.

Abstract: A semiconductor structure includes a via in contact with a conductive line and extending through a first etch stop layer, a first inter-metal dielectric layer, and a second etch stop layer. The second etch stop layer is disposed over the first inter-metal dielectric layer, and the first inter-metal dielectric layer is disposed over the first etch stop layer. The semiconductor structure also includes a trench in contact with the via and extending through an insulating layer and a second inter-metal dielectric layer. The second inter-metal dielectric layer is disposed over the insulating layer which is disposed over the second etch stop layer.

Abstract: A semiconductor interconnect structure includes a conductive line electrically coupled to an active semiconductor device, a first etch stop layer formed over the conductive line, a first dielectric layer formed over the first etch stop layer, a second etch stop layer formed over the first dielectric layer, a second dielectric layer formed over the second etch stop layer, and an interconnect structure electrically coupled to the via and extending through the first etch stop layer, the first dielectric layer, the second etch stop layer, and the second dielectric layer. The interconnect structure includes a via extending through the first etch stop layer, the second etch stop layer, and the first dielectric layer and a trench extending through the second dielectric layer.

Abstract: A method for forming an interconnect structure is described. In some embodiments, the method includes forming a mask structure on a dielectric layer, and the mask structure includes a first layer, a second layer disposed on the first layer, and a third layer disposed on the second layer. The method further includes forming first openings having first dimensions in the first layer and forming a multilayer structure over the first layer. The multilayer structure includes a bottom layer disposed in the first openings and over the first layer, a middle layer disposed on the bottom layer, and a photoresist layer disposed on the middle layer. The method further includes forming second openings having second dimensions in the bottom layer to expose portions of the dielectric layer, and the second dimensions are smaller than the first dimensions. The method further includes extending the second openings into the dielectric layer.

Abstract: An electronic device includes a motherboard, a bridging device, and an add-in card. The motherboard includes a processor, a first circuit board, and a first connector. The processor is coupled to the first connector through the first circuit board. The bridging device includes a second circuit board and a second connector and is disposed on the motherboard and coupled to the first connector. The second connector is coupled to the first connector through the second circuit board. The add-in card includes a third circuit board and a peripheral circuit and is disposed on the bridging device and coupled to the second connector. The peripheral circuit is coupled to the second connector through the third circuit board. The processor is coupled to the peripheral circuit through a signal path including the first circuit board, the first connector, the second circuit board, the second connector, and the third circuit board.

Abstract: A signal testing device and a signal testing method are provided. The method includes: obtaining, through a probe, a first frequency response corresponding to a test fixture and a device under test (DUT); obtaining, through the probe, a second frequency response corresponding to the test fixture; and generating a frequency response corresponding to the DUT according to the first frequency response, the second frequency response, a de-embedding algorithm, and an empirical mode decomposition algorithm.

Abstract: An electronic device includes a motherboard, a bridging device, and an add-in card. The motherboard includes a processor, a first circuit board, and a first connector. The processor is coupled to the first connector through the first circuit board. The bridging device includes a second circuit board and a second connector and is disposed on the motherboard and coupled to the first connector. The second connector is coupled to the first connector through the second circuit board. The add-in card includes a third circuit board and a peripheral circuit and is disposed on the bridging device and coupled to the second connector. The peripheral circuit is coupled to the second connector through the third circuit board. The processor is coupled to the peripheral circuit through a signal path including the first circuit board, the first connector, the second circuit board, the second connector, and the third circuit board.

Abstract: A circuit board for transmitting a high speed signal and for the high speed signal to be detected comprises a substrate, an insulating layer and two metal printed wires. The insulating layer is disposed on the substrate, and comprises a first surface, a second surface and a test opening, with the first surface facing away from the substrate, the second surface facing the substrate, and the test opening passing through the first surface and formed above the second surface. Said two metal printed wires are configured to transmit the high speed signal and embedded in the insulating layer between the first surface and the second surface. At least one of the metal printed wires comprises a test section which is aligned to the test opening of the insulating layer and exposed by the test opening.

Abstract: A circuit board for transmitting a high speed signal and for the high speed signal to be detected comprises a substrate, an insulating layer and two metal printed wires. The insulating layer is disposed on the substrate, and comprises a first surface, a second surface and a test opening, with the first surface facing away from the substrate, the second surface facing the substrate, and the test opening passing through the first surface and formed above the second surface. Said two metal printed wires are configured to transmit the high speed signal and embedded in the insulating layer between the first surface and the second surface. At least one of the metal printed wires comprises a test section which is aligned to the test opening of the insulating layer and exposed by the test opening.

Abstract: Disclosed herein is means for directly coupling a main motor shaft to a working machine with a coupling head as an intermediate component. The machine unit assembled according to the present invention does not require rechecking of dimensional deviations after completion of assembly. The present invention is applicable to both upright type and lateral type machine units.

Abstract: Disclosed herein is means for directly coupling main motor shaft to working machine with a coupling head as an intermediate component. By applying highly accurate precision machining technology. The machine unit assembled according to the present invention does not require recheck of dimensional deviation after completion of assembly. The present invention is applicable to both upright type and lateral type machine units.