Abstract: Integrated circuits, methods of forming integrated circuits, and methods of determining gate dielectric layer electrical thickness in integrated circuits are provided. An exemplary integrated circuit includes a semiconductor substrate including an active region and an STI structure disposed therein, adjacent to the active region. A first gate electrode structure overlies the active region and includes a first gate dielectric layer and a first gate electrode layer. A second gate electrode structure includes a second gate dielectric layer that overlies the first gate electrode layer and a second gate electrode layer that overlies the second gate dielectric layer. A source and drain region are formed in the active region, adjacent to the first gate electrode structure. First electrical interconnects are in electrical communication with the source and drain regions. A second electrical interconnect is in electrical communication with the first gate electrode layer.

Abstract: Methods for fabricating integrated circuits are disclosed. In an exemplary embodiment, a method for fabricating an integrated circuit includes forming a silicon material layer over a semiconductor substrate. The method further includes forming a capping layer over the silicon material layer and over the memory gate stack, removing the capping layer from over the memory array region and the high-voltage MOSFET region, forming a second silicon material layer over the capping layer and over the first silicon material layer, and removing the second silicon material layer. The method further includes removing the capping layer from over the first silicon material layer in the logic device region and removing the first and second silicon material layers from the high-voltage MOSFET region. Still further, the method includes forming a photoresist material layer over the memory array region and the logic device region and exposing the semiconductor substrate to an ion implantation process.

Abstract: Device and method for forming a device are presented. The method includes providing a substrate prepared with at least a memory cell region having first and second sub-regions and a logic region having input/output (I/O) region and core region. First voltage memory cell is formed in the first sub-region and second voltage memory cell is formed in the second sub-region of the memory cell region of the same substrate. The first voltage memory cell operates in a first voltage and the second voltage memory cell operates in a second voltage which is higher than the first voltage. Each of the first and second voltage memory cells includes a split gate having first and second gates. The first gate is a storage gate having a control gate over a floating gate and the second gate is a wordline. Logic I/O device is formed in the I/O region and logic core device is formed in the core region.

Abstract: Integrated circuits, methods of forming integrated circuits, and methods of determining gate dielectric layer electrical thickness in integrated circuits are provided. An exemplary integrated circuit includes a semiconductor substrate including an active region and an STI structure disposed therein, adjacent to the active region. A first gate electrode structure overlies the active region and includes a first gate dielectric layer and a first gate electrode layer. A second gate electrode structure includes a second gate dielectric layer that overlies the first gate electrode layer and a second gate electrode layer that overlies the second gate dielectric layer. A source and drain region are formed in the active region, adjacent to the first gate electrode structure. First electrical interconnects are in electrical communication with the source and drain regions. A second electrical interconnect is in electrical communication with the first gate electrode layer.

Abstract: Methods for fabricating integrated circuits are disclosed. In an exemplary embodiment, a method for fabricating an integrated circuit includes forming a silicon material layer over a semiconductor substrate. The method further includes forming a capping layer over the silicon material layer and over the memory gate stack, removing the capping layer from over the memory array region and the high-voltage MOSFET region, forming a second silicon material layer over the capping layer and over the first silicon material layer, and removing the second silicon material layer. The method further includes removing the capping layer from over the first silicon material layer in the logic device region and removing the first and second silicon material layers from the high-voltage MOSFET region. Still further, the method includes forming a photoresist material layer over the memory array region and the logic device region and exposing the semiconductor substrate to an ion implantation process.

Abstract: Methods for fabricating integrated circuits are disclosed. In an exemplary embodiment, a method for fabricating an integrated circuit includes forming a silicon material layer over a semiconductor substrate. The method further includes forming a capping layer over the silicon material layer and over the memory gate stack, removing the capping layer from over the memory array region and the high-voltage MOSFET region, forming a second silicon material layer over the capping layer and over the first silicon material layer, and removing the second silicon material layer. The method further includes removing the capping layer from over the first silicon material layer in the logic device region and removing the first and second silicon material layers from the high-voltage MOSFET region. Still further, the method includes forming a photoresist material layer over the memory array region and the logic device region and exposing the semiconductor substrate to an ion implantation process.

Abstract: Methods for fabricating integrated circuits are disclosed. In an exemplary embodiment, a method for fabricating an integrated circuit includes forming a silicon material layer over a semiconductor substrate. The method further includes forming a capping layer over the silicon material layer and over the memory gate stack, removing the capping layer from over the memory array region and the high-voltage MOSFET region, forming a second silicon material layer over the capping layer and over the first silicon material layer, and removing the second silicon material layer. The method further includes removing the capping layer from over the first silicon material layer in the logic device region and removing the first and second silicon material layers from the high-voltage MOSFET region. Still further, the method includes forming a photoresist material layer over the memory array region and the logic device region and exposing the semiconductor substrate to an ion implantation process.