Patents by Inventor Yi-Te Chiu
Yi-Te Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240412779Abstract: A pre-charge system includes a pre-charge circuit and a timing controller circuit. The pre-charge circuit performs time-division pre-charge upon a plurality of bit-line groups of a memory array according to a plurality of pre-charge timing control signals, wherein the memory array includes a plurality of memory cells each coupled to one of the plurality of bit-line groups. The timing controller circuit generates and outputs the plurality of pre-charge timing control signals to the pre-charge circuit.Type: ApplicationFiled: June 11, 2024Publication date: December 12, 2024Applicant: MEDIATEK INC.Inventors: Yi-Te Chiu, Ya-Ting Yang, Jia-Jing Chen
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Publication number: 20240312557Abstract: A memory with built-in synchronous-write-through (SWT) redundancy includes a plurality of memory input/output (IO) arrays, a plurality of SWT circuits, and at least one spare SWT circuit. The at least one spare SWT circuit is used to replace at least one of the plurality of SWT circuits that is defective.Type: ApplicationFiled: February 16, 2024Publication date: September 19, 2024Applicant: MEDIATEK INC.Inventors: Che-Wei Chou, Ya-Ting Yang, Shu-Lin Lai, Chi-Kai Hsieh, Yi-Ping Kuo, Chi-Hao Hong, Jia-Jing Chen, Yi-Te Chiu, Jiann-Tseng Huang
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Patent number: 11887660Abstract: The present invention provides a pseudo dual-port memory. The pseudo dual-port memory includes a single-port memory, a multiplexer, a timing control circuit and an output circuit. The multiplexer is configured to sequentially output a first address and a second address to the single-port memory. The output circuit is configured to receive output data from the single-port memory to generate a first reading result corresponding to the first address and a second reading result corresponding to the second address. The output circuit includes a first sense amplifier and a second sense amplifier, wherein the first sense amplifier receives the output data to generate first data serving as the first reading result according to a first control signal, and the second sense amplifier receives the output data to generate second data serving as the second reading result according to a second control signal.Type: GrantFiled: August 24, 2022Date of Patent: January 30, 2024Assignee: MEDIATEK INC.Inventors: Yi-Ping Kuo, Yi-Te Chiu
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Patent number: 11676657Abstract: The present invention provides a pseudo dual-port memory. The pseudo dual-port memory includes a single-port memory, a multiplexer, a timing control circuit and an output circuit. The multiplexer is configured to sequentially output a first address and a second address to the single-port memory. The output circuit is configured to receive output data from the single-port memory to generate a first reading result corresponding to the first address and a second reading result corresponding to the second address. The output circuit includes a first sense amplifier and a second sense amplifier, wherein the first sense amplifier receives the output data to generate first data serving as the first reading result according to a first control signal, and the second sense amplifier receives the output data to generate second data serving as the second reading result according to a second control signal.Type: GrantFiled: March 24, 2021Date of Patent: June 13, 2023Assignee: MEDIATEK INC.Inventors: Yi-Ping Kuo, Yi-Te Chiu
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Publication number: 20220406373Abstract: The present invention provides a pseudo dual-port memory. The pseudo dual-port memory includes a single-port memory, a multiplexer, a timing control circuit and an output circuit. The multiplexer is configured to sequentially output a first address and a second address to the single-port memory. The output circuit is configured to receive output data from the single-port memory to generate a first reading result corresponding to the first address and a second reading result corresponding to the second address. The output circuit includes a first sense amplifier and a second sense amplifier, wherein the first sense amplifier receives the output data to generate first data serving as the first reading result according to a first control signal, and the second sense amplifier receives the output data to generate second data serving as the second reading result according to a second control signal.Type: ApplicationFiled: August 24, 2022Publication date: December 22, 2022Applicant: MEDIATEK INC.Inventors: Yi-Ping Kuo, Yi-Te Chiu
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Publication number: 20220366116Abstract: An integrated circuit (IC) may include a plurality of functional blocks, and each functional block of the plurality of functional blocks may include hardware circuits, wherein the plurality of functional blocks may include a first functional block. In addition, the first functional block may include a first macro circuit that is positioned within a first sub-region of the first functional block, wherein among multiple sides of the first sub-region, a first side of the first sub-region is closest to a boundary of the first functional block. Additionally, a first intermediate sub-region of the first functional block is positioned between the first side of the first sub-region and the boundary of the first functional block, and there is no tap cell in the first intermediate sub-region of the first functional block.Type: ApplicationFiled: February 16, 2022Publication date: November 17, 2022Applicant: MEDIATEK INC.Inventors: Yu-Tung Chang, Yi-Chun Tsai, Tung-Kai Tsai, Yi-Te Chiu, Shih-Yun Lin, Hung-Ming Chu, Yi-Feng Chen
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Publication number: 20210327500Abstract: The present invention provides a pseudo dual-port memory. The pseudo dual-port memory includes a single-port memory, a multiplexer, a timing control circuit and an output circuit. The multiplexer is configured to sequentially output a first address and a second address to the single-port memory. The output circuit is configured to receive output data from the single-port memory to generate a first reading result corresponding to the first address and a second reading result corresponding to the second address. The output circuit includes a first sense amplifier and a second sense amplifier, wherein the first sense amplifier receives the output data to generate first data serving as the first reading result according to a first control signal, and the second sense amplifier receives the output data to generate second data serving as the second reading result according to a second control signal.Type: ApplicationFiled: March 24, 2021Publication date: October 21, 2021Inventors: Yi-Ping Kuo, Yi-Te Chiu
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Patent number: 10770161Abstract: A sense amplifier for reading a via Read-Only Memory (Via-ROM) is provided. The sense amplifier includes a read circuit, an adaptive keeper circuit and a leakage monitor circuit. The read circuit is connected to the via-ROM. The adaptive keeper circuit is connected to the read circuit. The leakage monitor circuit is connected to the adaptive keeper circuit for forming a current mirror, such that the adaptive keeper circuit compensates a read voltage of a memory cell whose via is opened when a bit-line leakage is happened.Type: GrantFiled: December 6, 2018Date of Patent: September 8, 2020Assignee: MEDIATEK INC.Inventors: Chia-Wei Wang, Shu-Lin Lai, Yi-Te Chiu
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Patent number: 10541023Abstract: A data line control circuit has a data line driving circuit and a write-assist data line driving circuit. The data line driving circuit is used to drive differential data lines during a write operation of at least one memory cell. The write-assist data line driving circuit is used to drive at least one write-assist data line during the write operation of the at least one memory cell, wherein the at least one write-assist data line is isolated from the differential data lines, and is driven to have a first voltage transition from a first voltage level to a second voltage level, such that one of the differential data lines has a second voltage transition from a third voltage level to a fourth voltage level that is induced by the first voltage transition via capacitive coupling.Type: GrantFiled: June 26, 2018Date of Patent: January 21, 2020Assignee: MEDIATEK INC.Inventors: Chia-Wei Wang, Yi-Te Chiu, Wen-Pin Hsieh
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Publication number: 20190108890Abstract: A sense amplifier for reading a via Read-Only Memory (Via-ROM) is provided. The sense amplifier includes a read circuit, an adaptive keeper circuit and a leakage monitor circuit. The read circuit is connected to the via-ROM. The adaptive keeper circuit is connected to the read circuit. The leakage monitor circuit is connected to the adaptive keeper circuit for forming a current mirror, such that the adaptive keeper circuit compensates a read voltage of a memory cell whose via is opened when a bit-line leakage is happened.Type: ApplicationFiled: December 6, 2018Publication date: April 11, 2019Inventors: Chia-Wei Wang, Shu-Lin Lai, Yi-Te Chiu
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Publication number: 20190074054Abstract: A data line control circuit has a data line driving circuit and a write-assist data line driving circuit. The data line driving circuit is used to drive differential data lines during a write operation of at least one memory cell. The write-assist data line driving circuit is used to drive at least one write-assist data line during the write operation of the at least one memory cell, wherein the at least one write-assist data line is isolated from the differential data lines, and is driven to have a first voltage transition from a first voltage level to a second voltage level, such that one of the differential data lines has a second voltage transition from a third voltage level to a fourth voltage level that is induced by the first voltage transition via capacitive coupling.Type: ApplicationFiled: June 26, 2018Publication date: March 7, 2019Inventors: Chia-Wei Wang, Yi-Te Chiu, Wen-Pin Hsieh
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Patent number: 10181358Abstract: A sense amplifier for reading a via Read-Only Memory (Via-ROM) is provided. The sense amplifier includes a read circuit, an adaptive keeper circuit and a leakage monitor circuit. The read circuit is connected to the via-ROM. The adaptive keeper circuit is connected to the read circuit. The leakage monitor circuit is connected to the adaptive keeper circuit for forming a current mirror, such that the adaptive keeper circuit compensates a read voltage of a memory cell whose via is opened when a bit-line leakage is happened.Type: GrantFiled: April 20, 2017Date of Patent: January 15, 2019Assignee: MEDIATEK INC.Inventors: Chia-Wei Wang, Shu-Lin Lai, Yi-Te Chiu
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Publication number: 20180114583Abstract: A sense amplifier for reading a via Read-Only Memory (Via-ROM) is provided. The sense amplifier includes a read circuit, an adaptive keeper circuit and a leakage monitor circuit. The read circuit is connected to the via-ROM. The adaptive keeper circuit is connected to the read circuit. The leakage monitor circuit is connected to the adaptive keeper circuit for forming a current mirror, such that the adaptive keeper circuit compensates a read voltage of a memory cell whose via is opened when a bit-line leakage is happened.Type: ApplicationFiled: April 20, 2017Publication date: April 26, 2018Inventors: Chia-Wei Wang, Shu-Lin Lai, Yi-Te Chiu
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Patent number: 9690365Abstract: A processing device performs dual-rail power equalization for its memory cell array and logic circuitry. The memory cell array is coupled to a first power rail through a first switch to receive a first voltage level. The logic circuitry is coupled to a second power rail through a second switch to receive a second voltage level that is different from the first voltage level. The processing device also includes a power switch coupled to at least the second power rail and operative to be enabled to equalize voltage supplied to the memory cell array and the logic circuitry.Type: GrantFiled: April 26, 2016Date of Patent: June 27, 2017Assignee: MediaTek, Inc.Inventors: Hugh Thomas Mair, Yi-Te Chiu, Che-Wei Wu, Lee-Kee Yong, Chia-Wei Wang, Cheng-Hsing Chien, Uming Ko
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Publication number: 20160320821Abstract: A processing device performs dual-rail power equalization for its memory cell array and logic circuitry. The memory cell array is coupled to a first power rail through a first switch to receive a first voltage level. The logic circuitry is coupled to a second power rail through a second switch to receive a second voltage level that is different from the first voltage level. The processing device also includes a power switch coupled to at least the second power rail and operative to be enabled to equalize voltage supplied to the memory cell array and the logic circuitry.Type: ApplicationFiled: April 26, 2016Publication date: November 3, 2016Inventors: Hugh Thomas Mair, Yi-Te Chiu, Che-Wei Wu, Lee-Kee Yong, Chia-Wei Wang, Cheng-Hsing Chien, Uming Ko
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Patent number: 8498174Abstract: An innovative dual-port subthreshold static random access memory (SRAM) cell for sub-threshold voltage operation is disclosed. During write mode, the dual-port subthreshold SRAM cell would cut off the positive feedback loop of the inverters and utilize the reverse short-channel effect to enhance write capability. The single-ended read/write port structure further reduces power consumption of the lengthy bit line. Therefore, the dual-port subthreshold SRAM cell is a suitable for long operation in a first-in first-out memory system. Although the lower voltage reduces the stability of the memory cell, the dual-port subthreshold SRAM cell of the present invention can still stably operate.Type: GrantFiled: September 23, 2011Date of Patent: July 30, 2013Assignee: National Chiao Tung UniversityInventors: Yi-Te Chiu, Ming-Hung Chang, Hao-I Yang, Wei Hwang
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Patent number: 8437178Abstract: A static random access memory cell includes a latch unit. The latch unit includes a bi-inverting circuit and a switching circuit. The bi-inverting circuit has a first terminal and a second terminal. The switching circuit is electrically connected between the first terminal and the second terminal, wherein when the switching circuit is turned on, the switching circuit forms a feedback between the first terminal and the second terminal for latching the latch unit; and when the switching circuit is turned off, the feedback is removed to cause the SRAM cell to write a data bit to the latch unit.Type: GrantFiled: April 28, 2011Date of Patent: May 7, 2013Assignee: National Chiao Tung UniversityInventors: Yi-Te Chiu, Ming-Hung Chang, Hao-I Yang, Wei Hwang
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Publication number: 20120307548Abstract: An innovative dual-port subthreshold static random access memory (SRAM) cell for sub-threshold voltage operation is disclosed. During write mode, the dual-port subthreshold SRAM cell would cut off the positive feedback loop of the inverters and utilize the reverse short-channel effect to enhance write capability. The single-ended read/write port structure further reduces power consumption of the lengthy bit line. Therefore, the dual-port subthreshold SRAM cell is a suitable for long operation in a first-in first-out memory system. Although the lower voltage reduces the stability of the memory cell, the dual-port subthreshold SRAM cell of the present invention can still stably operate.Type: ApplicationFiled: September 23, 2011Publication date: December 6, 2012Applicant: NATIONAL CHIAO TUNG UNIVERSITYInventors: Yi-Te Chiu, Ming-Hung Chang, Hao-I Yang, Wei Hwang
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Publication number: 20120230086Abstract: A static random access memory cell includes a latch unit. The latch unit includes a bi-inverting circuit and a switching circuit. The bi-inverting circuit has a first terminal and a second terminal. The switching circuit is electrically connected between the first terminal and the second terminal, wherein when the switching circuit is turned on, the switching circuit forms a feedback between the first terminal and the second terminal for latching the latch unit; and when the switching circuit is turned off, the feedback is removed to cause the SRAM cell to write a data bit to the latch unit.Type: ApplicationFiled: April 28, 2011Publication date: September 13, 2012Applicant: NATIONAL CHIAO TUNG UNIVERSITYInventors: Yi-Te Chiu, Ming-Hung Chang, Hao-I Yang, Wei Hwang