Abstract: The present disclosure provides a testing method and a testing system. The testing method is performed by at least one processor and includes the following operations: converting a circuit data of a scan test to a program, in which the program is configured to observe an untested part of a circuitry that is unable to be tested in the scan test; generating a waveform data associated with the untested part; generating a look-up table according to the program and a netlist file, in which the netlist file indicates the circuitry; and testing the untested part of the circuitry according to the waveform data and the look-up table.

Abstract: The present disclosure provides a testing method and a testing system. The testing method is performed by at least one processor and includes the following operations: converting a circuit data of a scan test to a program, in which the program is configured to observe an untested part of a circuitry that is unable to be tested in the scan test; generating a waveform data associated with the untested part; generating a look-up table according to the program and a netlist file, in which the netlist file indicates the circuitry; and testing the untested part of the circuitry according to the waveform data and the look-up table.

Abstract: A testing method is performed by at least one processor and includes following operations: converting first data associated with a scan test into a program, in which the program is configured to observe an untested part of a circuitry that is unable to be tested in the scan test; performing circuit simulations with the program according to a netlist file indicating the circuitry and testing patterns, in order to rank the testing patterns to generate second data; selecting at least one candidate testing pattern from the testing patterns according to the second data; and performing at least one fault simulation on the circuitry according to the netlist file and the at least one candidate testing pattern, in order to test the circuitry.

Abstract: For solving the defect that a hardware clock of a serial peripheral interface bus has to cooperate with slower software-simulated clocks used by a microprocessor while applying serial peripheral interface buses on a large-scale touch panel, a programmable logic device is used as a bridge of communicating information between the micro processor and sensors. Therefore, the microprocessor no longer has to take execution time to simulate serial peripheral interface buses by software, and is able to program hardware clocks of each of the serial peripheral interface buses according to speed requirements of different sensors, so that sensing signals of a plurality of sensors may be integrated on a touch device having the large-scale touch panel, and a processing speed of the touch device in processing the sensing signals may be optimized as a result.

Abstract: For solving the defect that a hardware clock of a serial peripheral interface bus has to cooperate with slower software-simulated clocks used by a microprocessor while applying serial peripheral interface buses on a large-scale touch panel, a programmable logic device is used as a bridge of communicating information between the micro processor and sensors. Therefore, the microprocessor no longer has to take execution time to simulate serial peripheral interface buses by software, and is able to program hardware clocks of each of the serial peripheral interface buses according to speed requirements of different sensors, so that sensing signals of a plurality of sensors may be integrated on a touch device having the large-scale touch panel, and a processing speed of the touch device in processing the sensing signals may be optimized as a result.