Abstract: A computer peripheral device is provided. The computer peripheral device is adapted to be installed in an electronic device supporting signal transmission of a first signal frequency. The computer peripheral device includes a human interface device (HID) and a bridging device. The HID includes a control unit to support signal transmission of a second signal frequency. The bridging device includes a first universal serial bus (USB) interface unit and a second USB interface unit. The first USB interface unit is adapted to be electrically connected to the electronic device, and supports signal transmission of the first signal frequency. The second USB interface unit is adapted to be electrically connected to the HID. The second USB interface unit regards the HID as a communication device class (CDC) device, instructs the control unit to generate an input signal at a timing corresponding to the first signal frequency, and transmits the input signal to the electronic device.

Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a first region and a second region, forming a first bottom barrier metal (BBM) layer on the first region and the second region, forming a first work function metal (WFM) layer on the first BBM layer on the first region and the second region, and then forming a diffusion barrier layer on the first WFM layer.

Abstract: An apparatus for PVD is provided. The apparatus includes a chamber, a pedestal disposed in the chamber to accommodate a wafer, and a ring. The ring includes a ring body having a first top surface and a second top surface, and a barrier structure disposed between the first top surface and the second top surface. The barrier structure can further include at least a first portion and a second portion separated from each other. The second vertical distance is equal to or greater than the first vertical distance.

Abstract: According to one aspect, intersection scenario description may be implemented by receiving a video stream of a surrounding environment of an ego-vehicle, extracting tracklets and appearance features associated with dynamic objects from the surrounding environment, extracting motion features associated with dynamic objects from the surrounding environment based on the corresponding tracklets, passing the appearance features through an appearance neural network to generate an appearance model, passing the motion features through a motion neural network to generate a motion model, passing the appearance model and the motion model through a fusion network to generate a fusion output, passing the fusion output through a classifier to generate a classifier output, and passing the classifier output through a loss function to generate a multi-label classification output associated with the ego-vehicle, dynamic objects, and corresponding motion paths.

Abstract: A semiconductor device includes a semiconductor fin. The semiconductor device includes a first silicon oxide layer contacting the semiconductor fin at a first interface and including nitrogen at a first concentration. The semiconductor device includes a second silicon oxide layer contacting the first silicon oxide layer at a second interface and including nitrogen at a second concentration that is greater than the first concentration.

Abstract: A MRAM circuit structure is provided in the present invention, with the unit cell composed of three transistors in series and four MTJs, wherein the junction between first transistor and third transistor is first node, the junction between second transistor and third transistor is second node, and the other ends of first transistor and third transistor are connected to a common source line. First MTJ is connected to second MTJ in series to form a first MTJ pair that connecting to the first node, and third MTJ is connected to fourth MTJ in series to form a second MTJ pair that connecting to the second node.

Abstract: A device includes a substrate, a first semiconductor fin over the substrate extending in a first lateral direction, a first vertical stack of semiconductor nanosheets over the substrate extending in the first lateral direction, and an inactive fin between the first semiconductor fin and the first vertical stack extending in the first lateral direction. A first gate structure surrounds and covers the first semiconductor fin, and extends in a second lateral direction substantially perpendicular to the first lateral direction. A second gate structure surrounds and covers the first vertical stack, and extends in the second lateral direction.

Abstract: A semiconductor device includes a supporting structure, a die stack, and a redistribution circuit structure. The die stack is disposed over the supporting structure and includes a first semiconductor die comprising a substrate and a second semiconductor die, where the first semiconductor die is between the second semiconductor die and the supporting structure, and a material of the supporting structure is different from a material of the substrate of the first semiconductor die. The redistribution circuit structure is disposed over the die stack and electrically coupled to the first semiconductor die and the second semiconductor die.

Abstract: A pre-charge system includes a pre-charge circuit and a timing controller circuit. The pre-charge circuit performs time-division pre-charge upon a plurality of bit-line groups of a memory array according to a plurality of pre-charge timing control signals, wherein the memory array includes a plurality of memory cells each coupled to one of the plurality of bit-line groups. The timing controller circuit generates and outputs the plurality of pre-charge timing control signals to the pre-charge circuit.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a functional cell region including an n-type functional transistor and a p-type functional transistor. The semiconductor structure also includes a first power transmission cell region including a first cutting feature and a first contact rail in the first cutting feature. The semiconductor structure also includes a first power rail electrically connected to a source terminal of the p-type functional transistor and the first contact rail of the first power transmission cell region. The semiconductor structure also includes a second power transmission cell region adjacent to the first power transmission cell and including a second cutting feature and second contact rail in the second cutting feature. The semiconductor structure also includes an insulating strip extending from the first cutting feature to the second cutting feature in a first direction.

Abstract: Middle-of-line (MOL) interconnects and corresponding techniques for forming the MOL interconnects are disclosed herein. An exemplary MOL interconnect structure includes a barrier-free source/drain contact, a barrier-free source/drain via, and a barrier-free gate via disposed in an insulator layer. The barrier-free source/drain is disposed on an epitaxial source/drain, and the barrier-free source/drain contact includes tungsten, molybdenum, or a combination thereof. The barrier-free source/drain via is disposed on the barrier-free source/drain contact and the barrier-free source/drain via includes molybdenum. The barrier-free gate via is disposed on a gate stack disposed adjacent to the epitaxial source/drain, and the barrier-free gate via includes tungsten, molybdenum, or a combination thereof. A width of the barrier-free source/drain via and/or the barrier-free gate via may be less than about 16 nm. The barrier-free source/drain via and/or the barrier-free gate via may be formed at the same time (e.g.

Abstract: The present disclosure relates to a force measuring device (1) comprising a spring module (2), and an electronic module (3), detachably mechanically connected to the spring module. The spring module comprises a test head (21) defining an outer surface of the device, a spring seat (23), and a spring (24) arranged between the test head and the spring seat, with a first end (24a) of the spring engaging the test head and a second end (24b) of the spring engaging the spring seat. The electronic module comprises a force sensor (31) arranged in physical contact with the spring seat.

Abstract: A semiconductor device includes a plurality of semiconductor fins, at least one gate stack, a refill isolation, and an air gap. Each of the semiconductor fins extends in an X direction. Two adjacent ones of the semiconductor fins are spaced apart from each other in a Y direction transverse to the X direction. The at least one gate stack has two stack sections spaced apart from each other in the Y direction. The stack sections are disposed over two adjacent ones of the semiconductor fins, respectively. The refill isolation and the air gap are disposed between the stack sections.

Abstract: A method includes forming a dielectric layer over an epitaxial source/drain region. An opening is formed in the dielectric layer. The opening exposes a portion of the epitaxial source/drain region. A barrier layer is formed on a sidewall and a bottom of the opening. An oxidation process is performing on the sidewall and the bottom of the opening. The oxidation process transforms a portion of the barrier layer into an oxidized barrier layer and transforms a portion of the dielectric layer adjacent to the oxidized barrier layer into a liner layer. The oxidized barrier layer is removed. The opening is filled with a conductive material in a bottom-up manner. The conductive material is in physical contact with the liner layer.

Abstract: In an embodiment, a device includes: a first interconnect structure including metallization patterns; a second interconnect structure including a power rail; a device layer between the first interconnect structure and the second interconnect structure, the device layer including a first transistor, the first transistor including an epitaxial source/drain region; and a conductive via extending through the device layer, the conductive via connecting the power rail to the metallization patterns, the conductive via contacting the epitaxial source/drain region.

Abstract: A temperature measuring apparatus for measuring a temperature of a substrate is described. A light emitting source that emits light signals such as laser pulses are applied to the substrate. A detector on the other side of the light emitting source receives the reflected laser pulses. The detector further receives emission signals associated with temperature or energy density that is radiated from the surface of the substrate. The temperature measuring apparatus determines the temperature of the substrate during a thermal process using the received laser pulses and the emission signals. To improve the signal to noise ratio of the reflected laser pulses, a polarizer may be used to polarize the laser pulses to have a S polarization. The angle in which the polarized laser pulses are applied towards the substrate may also be controlled to enhance the signal to noise ratio at the detector's end.

Abstract: A semiconductor device includes a plurality of semiconductor fins, at least one gate stack, a refill isolation, and an air gap. Each of the semiconductor fins extends in an X direction. Two adjacent ones of the semiconductor fins are spaced apart from each other in a Y direction transverse to the X direction. The at least one gate stack has two stack sections spaced apart from each other in the Y direction. The stack sections are disposed over two adjacent ones of the semiconductor fins, respectively. The refill isolation and the air gap are disposed between the stack sections.

Abstract: In an embodiment, a device includes: a first interconnect structure including metallization patterns; a second interconnect structure including a power rail; a device layer between the first interconnect structure and the second interconnect structure, the device layer including a first transistor, the first transistor including an epitaxial source/drain region; and a conductive via extending through the device layer, the conductive via connecting the power rail to the metallization patterns, the conductive via contacting the epitaxial source/drain region.

Abstract: A projection device including an imaging module, a freeform-surface reflective mirror, and a projection lens assembly is provided. The imaging module is configured to provide imaging beams and includes a display panel and a light-source module. The imaging beams are transmitted toward the projection lens assembly by the freeform-surface reflective mirror. The projection lens assembly includes a first optical axis and a second optical axis. The first optical axis passes through the projection lens assembly. The imaging beams emitted by the projection device form an imaging-beam region, in which the first optical axis does not pass through a geometric center of the imaging-beam region, and the second optical axis passes through a geometric center region of the display panel. The geometric center region is a region having a distance less than or equal to 40% of a minimum width of the display panel from a geometric center of the display panel.

Abstract: A method and apparatus for minimizing silicon germanium facets in planar metal oxide semiconductor structures is disclosed. For example, a device fabricated according to the method may include a semiconductor substrate, a plurality of gate stacks formed on the substrate, a plurality of source/drain regions formed from silicon germanium, and a shallow trench isolation region positioned between two source/drain regions of the plurality of source/drain regions. Each source/drain region of the plurality of source/drain regions is positioned adjacent to at least one gate stack of the plurality of gate stacks. Moreover, the shallow trench isolation region forms a trench in the substrate without intersecting the two source/drain regions.