Patents by Inventor Yi-Ting Chen

Yi-Ting Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250087533
    Abstract: A method of forming a semiconductor device includes: forming a via in a first dielectric layer disposed over a substrate; forming a second dielectric layer over the first dielectric layer; forming an opening in the second dielectric layer, where the opening exposes an upper surface of the via; selectively forming a capping layer over the upper surface of the via, where the capping layer has a curved upper surface that extends above a first upper surface of the first dielectric layer distal from the substrate; after forming the capping layer, forming a barrier layer in the opening over the capping layer and along sidewalls of the second dielectric layer exposed by the opening; and filling the opening by forming an electrically conductive material over the barrier layer.
    Type: Application
    Filed: March 28, 2024
    Publication date: March 13, 2025
    Inventors: Ming-Hsing Tsai, Ya-Lien Lee, Chih-Han Tseng, Kuei-Wen Huang, Kuan-Hung Ho, Ming-Uei Hung, Chih-Cheng Kuo, Yi-An Lai, Wei-Ting Chen
  • Patent number: 12249649
    Abstract: A semiconductor device includes a fin-shaped structure on the substrate, a shallow trench isolation (STI) around the fin-shaped structure, a single diffusion break (SDB) structure in the fin-shaped structure for dividing the fin-shaped structure into a first portion and a second portion; a first gate structure on the fin-shaped structure, a second gate structure on the STI, and a third gate structure on the SDB structure. Preferably, a width of the third gate structure is greater than a width of the second gate structure and each of the first gate structure, the second gate structure, and the third gate structure includes a U-shaped high-k dielectric layer, a U-shaped work function metal layer, and a low-resistance metal layer.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: March 11, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Cheng-Han Wu, Hsin-Yu Chen, Chun-Hao Lin, Shou-Wei Hsieh, Chih-Ming Su, Yi-Ren Chen, Yuan-Ting Chuang
  • Publication number: 20250081650
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a first epitaxial layer over the substrate, a first photodiode and a second photodiode in the first epitaxial layer, and a trench isolation structure between the first photodiode and the second photodiode. The first photodiode includes a first doped region having a first conductivity type. The first photodiode includes a second doped region, overlying the first doped region, having a second conductivity type different than the first conductivity type. The first photodiode includes a third doped region, overlying the first doped region, having the second conductivity type. A first distance between a sidewall of the third doped region and an uppermost surface of the first epitaxial layer is between about a hundredth to about a fifth of a second distance between a sidewall of the trench isolation structure and the uppermost surface of the first epitaxial layer.
    Type: Application
    Filed: August 28, 2023
    Publication date: March 6, 2025
    Inventors: Wen-Sheng WANG, Yi-Hsuan Fan, Yen-Ting Chen
  • Publication number: 20250076245
    Abstract: A method and system for establishing a model for sensing ions in a solution, and a method and system for sensing ions in a solution apply an ion-sensitive field effect transistor in a machine learning model for ion detection in training solutions. The method for establishing a model includes adjusting environmental parameters, where the environmental parameters are selected from any one of multiple target temperatures or from any one of multiple external electric fields; establishing at least one virtual sensor based on the biasing relationship of the multi-gate ion sensitive field effect transistor; obtaining, by the at least one virtual sensor, multiple training features of the training solution based on the environmental parameters and bias parameters; and loading, by a computer, the environmental parameters and the training features into a machine learning model to establish an ion detection model, which is used to sense the types and concentrations of ions.
    Type: Application
    Filed: November 9, 2023
    Publication date: March 6, 2025
    Inventors: Chih-Ting Lin, Yi-Ting Wu, Sheng-Yu Chen, Wei-En Hsu
  • Patent number: 12243782
    Abstract: The present disclosure describes fabricating devices with tunable gate height and effective capacitance. A method includes forming a first metal gate stack in a dummy region of a semiconductor substrate and a second metal gate stack in an active device region of the semiconductor substrate, and performing a chemical mechanical polishing (CMP) process using a slurry including charged abrasive nanoparticles. The first and second metal gate stacks are different in composition. The charged abrasive nanoparticles include a first concentration in the active device region different from a second concentration in the dummy region.
    Type: Grant
    Filed: August 4, 2023
    Date of Patent: March 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING C0., LTD.
    Inventors: Ming-Chang Wen, Chang-Yun Chang, Keng-Yao Chen, Chen-Yu Tai, Yi-Ting Fu
  • Publication number: 20250072007
    Abstract: A MRAM layout structure with multiple unit cells, including a first word line, a second word line and a third word line extending through active areas, wherein two ends of a first MTJ are connected respectively to a second active area and one end of a second MTJ, and two ends of a third MTJ are connected respectively to a third active area and one end of a fourth MTJ, and a first bit line and a second bit line connected respectively to the other end of the second MTJ and the other end of the fourth MTJ.
    Type: Application
    Filed: November 13, 2024
    Publication date: February 27, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Ting Wu, Cheng-Tung Huang, Jen-Yu Wang, Yung-Ching Hsieh, Po-Chun Yang, Jian-Jhong Chen, Bo-Chang Li
  • Patent number: 12237394
    Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a first region and a second region, forming a first bottom barrier metal (BBM) layer on the first region and the second region, forming a first work function metal (WFM) layer on the first BBM layer on the first region and the second region, and then forming a diffusion barrier layer on the first WFM layer.
    Type: Grant
    Filed: July 26, 2023
    Date of Patent: February 25, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Fan Li, Wen-Yen Huang, Shih-Min Chou, Zhen Wu, Nien-Ting Ho, Chih-Chiang Wu, Ti-Bin Chen
  • Patent number: 12235615
    Abstract: A static auto-tuning system and method for controlling operation of a motor in a system. A speed reference signal is generated resulting in a speed response of the motor. Closed-loop feedback magnifies the rotating friction effect to an observable level. Inertia and rotating friction coefficient values of the system are estimated based on the speed frequency response and a virtual damping coefficient. A fixed low frequency speed signal may result in a first frequency response function for determining virtual damping, and a variable frequency excitation signal may result in a second frequency response function for determining the inertia and rotating friction characteristics. Closed-loop gains are determined based on these characteristics. The excitation signal may be sampled and a peak value in each interval may be identified and stored to produce an envelope of peak values for determining the gain response. Operation of the motor is controlled using the determined gains.
    Type: Grant
    Filed: October 14, 2022
    Date of Patent: February 25, 2025
    Inventors: Athanasios Sarigiannidis, Bo-Ting Lyu, Yi-Chieh Chen, Shih-Chin Yang
  • Publication number: 20250061005
    Abstract: A method for dynamic adaptive threading is provided. The method comprises receiving a query request for a recommended number of threads from an application. The method comprises determining the recommended number of threads according to a resource status of a system-on-a-chip (SoC) platform. The method comprises transmitting the recommended number of threads to the application.
    Type: Application
    Filed: August 15, 2024
    Publication date: February 20, 2025
    Inventors: Chung-Yang CHEN, Cheng-Che CHEN, Chung-Hao HO, Yi-Wei HO, Yen-Po CHIEN, Yen-Ting PAN
  • Publication number: 20250044544
    Abstract: An optical element driving mechanism is provided, which includes a movable assembly, a fixed portion, a driving assembly, and an adhesive element. The movable assembly is used for connecting an optical element. The movable assembly is movable relative to the fixed portion. The fixed portion includes a case and a bottom. The driving assembly is used for driving the movable assembly to move relative to the fixed portion. The case is affixed on the bottom through the adhesive element.
    Type: Application
    Filed: July 31, 2024
    Publication date: February 6, 2025
    Inventors: Kai-Po FAN, Man-Ting LU, Yi-Ho CHEN
  • Publication number: 20250044604
    Abstract: An optical element driving mechanism is provided, which includes a movable assembly, a fixed portion, a driving assembly, and a circuit assembly. The movable assembly is used for connecting an optical element. The movable assembly is movable relative to the fixed portion. The driving assembly is used for driving the movable assembly to move relative to the fixed portion. The circuit assembly connects the movable assembly and the fixed portion.
    Type: Application
    Filed: July 31, 2024
    Publication date: February 6, 2025
    Inventors: Kai-Po FAN, Man-Ting LU, Yi-Ho CHEN
  • Publication number: 20250044605
    Abstract: An optical element driving mechanism is provided, which includes a movable assembly, a fixed portion, and a driving assembly. The movable assembly is used for connecting an optical element. The movable assembly is movable relative to the fixed portion. The driving assembly is used for driving the movable assembly to move relative to the fixed portion.
    Type: Application
    Filed: July 31, 2024
    Publication date: February 6, 2025
    Inventors: Kai-Po FAN, Man-Ting LU, Yi-Ho CHEN
  • Publication number: 20250037858
    Abstract: The present invention disclose a medical image-based system for predicting lesion classification and a method thereof. The system comprises a feature data extracting module for providing a raw feature data based on a medical image, and a predicting module for outputting a predicted class and a risk index according to the raw feature data. The predicting module comprises a classification unit for generating the predicted class and a prediction score corresponding thereto according to the raw feature data, and a risk evaluation unit for generating the risk index according to the prediction score. The system provides medical personnels a reference score and a risk index to determine progression of a certain disease.
    Type: Application
    Filed: February 1, 2024
    Publication date: January 30, 2025
    Inventors: YI-SHAN TSAI, YU-HSUAN LAI, CHENG-SHIH LAI, CHAO-YUN CHEN, MENG-JHEN WU, YI-CHUAN LIN, YI-TING CHIANG, PENG-HAO FANG, PO-TSUN KUO, YI-CHIH CHIU
  • Publication number: 20250036977
    Abstract: An electronic device is configured to execute instructions: compiling a first AI model and second AI model(s) to a first compiled file and second compiled file(s), respectively, wherein the first compiled file comprises a first data set and a first command set, and the second compiled file(s) comprises second data set(s) and second command set(s); generating light version file(s) for the AI model(s), wherein the light version file(s) comprises the second command set(s) and data patch(es); storing the first compiled file and the light version file(s) to a storage device; loading the first compiled file from the storage device to a memory; loading the light version file(s) from the storage device to the memory; generating the second data set(s) according to the first data set and the data patch(es); and executing the second AI model(s) according to the generated second data set(s) and the second command set(s) in the memory.
    Type: Application
    Filed: June 23, 2024
    Publication date: January 30, 2025
    Applicant: MEDIATEK INC.
    Inventors: Chia-Wei Hsu, Yu-Lung Lu, Yen-Ting Chiang, Chih-wei Chen, Yi-Cheng Lu, Jia-Sian Hong, Kuan-Yu Chen, Pei-Kuei Tsung, Hua Wu
  • Publication number: 20250035890
    Abstract: An optical lens system includes six lens elements from an object side to an image side, the six lens elements are, in order from the object side to the image side, a first lens element, a second lens element, a third lens element, a fourth lens element, a fifth lens element and a sixth lens element. Each of the six lens elements has an object-side surface towards the object side and an image-side surface towards the image side. The image-side surface of the second lens element is concave in a paraxial region thereof. The third lens element has positive refractive power. The image-side surface of the fourth lens element is concave in a paraxial region thereof. The image-side surface of the sixth lens element includes at least one inflection point.
    Type: Application
    Filed: May 31, 2024
    Publication date: January 30, 2025
    Inventors: Kuan-Ting YEH, Shih-Han CHEN, Yi-Cheng LIN, Hsin-Hsuan HUANG, Yu-Han SHIH
  • Patent number: 12211790
    Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a first vertical structure and a second vertical structure formed over the substrate, and a conductive rail structure between the first and second vertical structures. A top surface of the conductive rail structure can be substantially coplanar with top surfaces of the first and the second vertical structures.
    Type: Grant
    Filed: August 10, 2023
    Date of Patent: January 28, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Bo Liao, Wei Ju Lee, Cheng-Ting Chung, Hou-Yu Chen, Chun-Fu Cheng, Kuan-Lun Cheng
  • Patent number: 12205854
    Abstract: The present disclosure provides an electronic device including a redistribution layer, a plurality of passive components, and an electronic component. The redistribution layer includes a first insulating layer, a second insulating layer, and a plurality of traces electrically connected to each other through a first opening of the first insulating layer and a second opening of the second insulating layer, wherein the first insulating layer has a first side away from the second insulating layer, and the second insulating layer has a second side away from the first insulating layer. The passive components are disposed on the first side. The electronic component is disposed on the second side. The plurality of passive components are electrically connected to the electronic component through the plurality of traces.
    Type: Grant
    Filed: September 19, 2023
    Date of Patent: January 21, 2025
    Assignee: InnoLux Corporation
    Inventors: Yeong-E Chen, Kuang-Chiang Huang, Yu-Ting Liu, Yi-Hung Lin, Cheng-En Cheng
  • Patent number: 12183090
    Abstract: According to one aspect, intersection scenario description may be implemented by receiving a video stream of a surrounding environment of an ego-vehicle, extracting tracklets and appearance features associated with dynamic objects from the surrounding environment, extracting motion features associated with dynamic objects from the surrounding environment based on the corresponding tracklets, passing the appearance features through an appearance neural network to generate an appearance model, passing the motion features through a motion neural network to generate a motion model, passing the appearance model and the motion model through a fusion network to generate a fusion output, passing the fusion output through a classifier to generate a classifier output, and passing the classifier output through a loss function to generate a multi-label classification output associated with the ego-vehicle, dynamic objects, and corresponding motion paths.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: December 31, 2024
    Assignee: HONDA MOTOR CO., LTD.
    Inventors: Nakul Agarwal, Yi-Ting Chen
  • Publication number: 20240429317
    Abstract: A semiconductor device includes a semiconductor fin. The semiconductor device includes a first silicon oxide layer contacting the semiconductor fin at a first interface and including nitrogen at a first concentration. The semiconductor device includes a second silicon oxide layer contacting the first silicon oxide layer at a second interface and including nitrogen at a second concentration that is greater than the first concentration.
    Type: Application
    Filed: June 26, 2023
    Publication date: December 26, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiao Po-Kai, Cheng-Wei Chen, Yi-Ting Chen, Pei Tsang Ho, Wei-Yang Tseng
  • Publication number: 20240363752
    Abstract: A method and apparatus for minimizing silicon germanium facets in planar metal oxide semiconductor structures is disclosed. For example, a device fabricated according to the method may include a semiconductor substrate, a plurality of gate stacks formed on the substrate, a plurality of source/drain regions formed from silicon germanium, and a shallow trench isolation region positioned between two source/drain regions of the plurality of source/drain regions. Each source/drain region of the plurality of source/drain regions is positioned adjacent to at least one gate stack of the plurality of gate stacks. Moreover, the shallow trench isolation region forms a trench in the substrate without intersecting the two source/drain regions.
    Type: Application
    Filed: July 8, 2024
    Publication date: October 31, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Sin WANG, Shan-Yun CHENG, Ching-Hung KAO, Jing-Jyu CHOU, Yi-Ting CHEN