Abstract: A traffic patterned-based modem function adjustment method includes receiving at least one traffic pattern by a user device, identifying the at least one traffic pattern by the user device for detecting a traffic mode of the user device, acquiring assisted information of the at least one traffic pattern by the user device, and adjusting at least one modem function according to the traffic mode and the assisted information. The at least one traffic pattern includes packet transmission characteristics, a radio signal status, and/or codec information of a network communicating with the user device.

Abstract: A method includes forming a semiconductive channel structure over a substrate. A semiconductive layer is deposited over the semiconductive channel structure. The semiconductive layer and the semiconductive channel structure includes different materials. An oxidation process is performed to the semiconductive layer to form an oxidation layer over a remaining portion of the semiconductive layer. The oxidation layer is heated after the oxidation process is performed. A gate structure is formed over the oxidation layer.

Abstract: A method includes forming a semiconductive channel layer on a substrate. A dummy gate is formed on the semiconductive channel layer. Gate spacers are formed on opposite sides of the dummy gate. The dummy gate is removed to form a gate trench between the gate spacers, resulting in the semiconductive channel layer exposed in the gate trench. A semiconductive protection layer is deposited in the gate trench and on the exposed semiconductive channel layer. A top portion of the semiconductive protection layer is oxidized to form an oxidation layer over a remaining portion of the semiconductive protection layer. The oxidation layer is annealed after the top portion of the semiconductive protection layer is oxidized. A gate structure is formed over the semiconductive protection layer and in the gate trench after the oxidation layer is annealed.

Abstract: A semiconductor device includes a substrate, a semiconductor fin, a silicon layer, a gate structure, gate spacers, and source/drain structures. The semiconductor fin is over the substrate. The silicon layer is over the semiconductor fin. The gate structure is over the silicon layer, in which the gate structure includes an interfacial layer over the silicon layer, a gate dielectric layer over the interfacial layer, and a gate electrode over the gate dielectric layer. The gate spacers are on opposite sidewalls of the gate structure and in contact with the interfacial layer of the gate structure, in which a bottom surface of the interfacial layer is higher than bottom surfaces of the gate spacers. The source/drain structures are on opposite sides of the gate structure.

Abstract: A semiconductor device includes a substrate, a semiconductor fin, a silicon layer, a gate structure, gate spacers, and source/drain structures. The semiconductor fin is over the substrate. The silicon layer is over the semiconductor fin. The gate structure is over the silicon layer, in which the gate structure includes an interfacial layer over the silicon layer, a gate dielectric layer over the interfacial layer, and a gate electrode over the gate dielectric layer. The gate spacers are on opposite sidewalls of the gate structure and in contact with the interfacial layer of the gate structure, in which a bottom surface of the interfacial layer is higher than bottom surfaces of the gate spacers. The source/drain structures are on opposite sides of the gate structure.

Abstract: User equipment (UE) for managing out-of-order packets is provided. The UE may include a radio frequency (RF) signal processing device, a management module, a filter module and a multi-reorder queue circuit. The RF signal processing device may receive a plurality of packets from a network node. The management module may collect network information of the network node and application information and generate a plurality of filter rules according to the network information and the application information. The filter module may receive the filter rules from the management module and allocate a plurality of out-of-order packets of the packets to different reorder queues according to the filter rules, wherein each reorder queue corresponds to a different reorder timer. The multi-reorder queue circuit includes the reorder queues. The multi-reorder queue circuit determines how to push each out-of-order packet to its corresponding application through a TCP/IP stack.

Abstract: A timing control management method includes receiving a real-time protocol (RTP) packet by a jitter buffer management module, generating a playout delay range according to the RTP packet, transmitting the playout delay range to a reordering timer management module, generating a timer adjustment command from the reordering timer management module to a transport layer reordering function module, and adjusting a reordering timer according to the playout delay range by the transport layer reordering function module after the timer adjustment command is received by the transport layer reordering function module.

Abstract: A semiconductor device includes a substrate, a semiconductor fin, a silicon layer, a gate structure, gate spacers, and source/drain structures. The semiconductor fin is over the substrate. The silicon layer is over the semiconductor fin. The gate structure is over the silicon layer, in which the gate structure includes an interfacial layer over the silicon layer, a gate dielectric layer over the interfacial layer, and a gate electrode over the gate dielectric layer. The gate spacers are on opposite sidewalls of the gate structure and in contact with the interfacial layer of the gate structure, in which a bottom surface of the interfacial layer is higher than bottom surfaces of the gate spacers. The source/drain structures are on opposite sides of the gate structure.

Abstract: A semiconductor device includes a substrate, a semiconductor fin, a silicon layer, a gate structure, gate spacers, and source/drain structures. The semiconductor fin is over the substrate. The silicon layer is over the semiconductor fin. The gate structure is over the silicon layer, in which the gate structure includes an interfacial layer over the silicon layer, a gate dielectric layer over the interfacial layer, and a gate electrode over the gate dielectric layer. The gate spacers are on opposite sidewalls of the gate structure and in contact with the interfacial layer of the gate structure, in which a bottom surface of the interfacial layer is higher than bottom surfaces of the gate spacers. The source/drain structures are on opposite sides of the gate structure.

Abstract: User equipment (UE) for managing out-of-order packets is provided. The UE may include a radio frequency (RF) signal processing device, a management module, a filter module and a multi-reorder queue circuit. The RF signal processing device may receive a plurality of packets from a network node. The management module may collect network information of the network node and application information and generate a plurality of filter rules according to the network information and the application information. The filter module may receive the filter rules from the management module and allocate a plurality of out-of-order packets of the packets to different reorder queues according to the filter rules, wherein each reorder queue corresponds to a different reorder timer. The multi-reorder queue circuit includes the reorder queues. The multi-reorder queue circuit determines how to push each out-of-order packet to its corresponding application through a TCP/IP stack.

Abstract: A method includes forming a semiconductive channel layer on a substrate. A dummy gate is formed on the semiconductive channel layer. Gate spacers are formed on opposite sides of the dummy gate. The dummy gate is removed to form a gate trench between the gate spacers, resulting in the semiconductive channel layer exposed in the gate trench. A semiconductive protection layer is deposited in the gate trench and on the exposed semiconductive channel layer. A top portion of the semiconductive protection layer is oxidized to form an oxidation layer over a remaining portion of the semiconductive protection layer. The oxidation layer is annealed after the top portion of the semiconductive protection layer is oxidized. A gate structure is formed over the semiconductive protection layer and in the gate trench after the oxidation layer is annealed.

Abstract: A semiconductor device includes a substrate, a semiconductor fin, a silicon layer, a gate structure, gate spacers, and source/drain structures. The semiconductor fin is over the substrate. The silicon layer is over the semiconductor fin. The gate structure is over the silicon layer, in which the gate structure includes an interfacial layer over the silicon layer, a gate dielectric layer over the interfacial layer, and a gate electrode over the gate dielectric layer. The gate spacers are on opposite sidewalls of the gate structure and in contact with the interfacial layer of the gate structure, in which a bottom surface of the interfacial layer is higher than bottom surfaces of the gate spacers. The source/drain structures are on opposite sides of the gate structure.

Abstract: A semiconductor device includes a semiconductive channel region, a semiconductive protection layer, a gate structure, and a pair of gate spacers. The semiconductive protection layer is on and in contact with the channel. The gate structure is above the semiconductive protection layer and includes gate dielectric layer and a gate electrode. The gate dielectric layer is above the semiconductive protection layer. The gate electrode is above the gate dielectric layer. The gate spacers are on opposite sides of the gate structure. The semiconductive protection layer extends from an inner sidewall of a first one of the pair of gate spacers to an inner sidewall of a second one of the pair of gate spacers.

Abstract: A semiconductor device includes a semiconductive channel region, a semiconductive protection layer, a gate structure, and a pair of gate spacers. The semiconductive protection layer is on and in contact with the channel. The gate structure is above the semiconductive protection layer and includes gate dielectric layer and a gate electrode. The gate dielectric layer is above the semiconductive protection layer. The gate electrode is above the gate dielectric layer. The gate spacers are on opposite sides of the gate structure. The semiconductive protection layer extends from an inner sidewall of a first one of the pair of gate spacers to an inner sidewall of a second one of the pair of gate spacers.

Abstract: A communications apparatus includes a radio transceiver and a processor. The radio transceiver transmits or receives wireless radio frequency signals to communicate with a first network device. The processor estimates a period for the first network device to transmit a timing advance (TA) command according to a plurality of previously received TA commands, determines an arrival time of a forthcoming TA command according to the estimated period, determines whether to skip a chance to receive the forthcoming TA command at the arrival time according to the estimated period and a TA timer interval, and does not use the radio transceiver to receive the forthcoming TA command at the arrival time when determining to skip the chance to receive the forthcoming TA command.

Abstract: A wafer and a forming method thereof are provided. The wafer has a die region and a scribe-line region adjacent to the die region, and includes a conductive bonding pad in the die region of the wafer and a wafer acceptance test (WAT) pad in the scribe-line region of the wafer. A top surface of the WAT pad is lower than a top surface of the conductive bonding pad.

Abstract: The wireless communication methods and devices are provided. The wireless communication method includes the steps of determining whether uplink data for an uplink transmission includes control messages; and forbidding a Tx power throttling procedure from being performed when the uplink data includes the control messages. When the uplink data does not include the control message the transmission power throttling procedure is performed.

Abstract: A wafer and a forming method thereof are provided. The wafer has a die region and a scribe-line region adjacent to the die region, and includes a conductive bonding pad in the die region of the wafer and a wafer acceptance test (WAT) pad in the scribe-line region of the wafer. A top surface of the WAT pad is lower than a top surface of the conductive bonding pad.

Abstract: A method of selecting an active SIM from multiple SIMs and a wireless device utilizing the same are disclosed. The method includes: acquiring SIM information associated with each SIM under a dynamic environment, wherein each SIM provides for the PS data service; calculating a SIM score of each SIM based on the acquired SIM information associated with each SIM; and selecting the active SIM based on all SIM scores to provide for the PS data service. The SIM information includes RSSI, RSCP, Ec/N0, CQI, and data speed on each SIM in the dynamic environment.

Abstract: An embodiment of a method for call management, performed by a processing unit of a UE (user equipment), is disclosed. The method is employed in a hardware configuration of at least two subscriber identity cards sharing a radio resource. A PS (packet-switched) service is first provided for the first subscriber identity card. Packet data transmission and reception is handed over to a second PS service with the second subscriber identity card from the first PS service after receiving a call request requesting a CS (circuit-switched) service with the second subscriber identity card.