Patents by Inventor Yi-Ting Fu
Yi-Ting Fu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230386927Abstract: The present disclosure describes fabricating devices with tunable gate height and effective capacitance. A method includes forming a first metal gate stack in a dummy region of a semiconductor substrate and a second metal gate stack in an active device region of the semiconductor substrate, and performing a chemical mechanical polishing (CMP) process using a slurry including charged abrasive nanoparticles. The first and second metal gate stacks are different in composition. The charged abrasive nanoparticles include a first concentration in the active device region different from a second concentration in the dummy region.Type: ApplicationFiled: August 4, 2023Publication date: November 30, 2023Inventors: Ming-Chang Wen, Chang-Yun Chang, Keng-Yao Chen, Chen-Yu Tai, Yi-Ting Fu
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Patent number: 11817354Abstract: The present disclosure describes fabricating devices with tunable gate height and effective capacitance. A method includes forming a first metal gate stack in a dummy region of a semiconductor substrate, the first metal gate stack including a first work function metal (WFM) layer; forming a second metal gate stack in an active device region of the semiconductor substrate, the second metal gate stack including a second WFM layer different than the first WFM layer; and performing a CMP process using a slurry including charged abrasive nanoparticles. The charged abrasive nanoparticles include a first concentration in the active device region different from a second concentration in the dummy region causing different polish rates in the active device region and dummy region. After the performing of the CMP process, the first metal gate stack has a first height different from a second height of the second metal gate stack.Type: GrantFiled: August 9, 2022Date of Patent: November 14, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Ming-Chang Wen, Chang-Yun Chang, Keng-Yao Chen, Chen-Yu Tai, Yi-Ting Fu
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Publication number: 20230268347Abstract: A semiconductor device includes a plurality of semiconductor fins, at least one gate stack, a refill isolation, and an air gap. Each of the semiconductor fins extends in an X direction. Two adjacent ones of the semiconductor fins are spaced apart from each other in a Y direction transverse to the X direction. The at least one gate stack has two stack sections spaced apart from each other in the Y direction. The stack sections are disposed over two adjacent ones of the semiconductor fins, respectively. The refill isolation and the air gap are disposed between the stack sections.Type: ApplicationFiled: April 27, 2023Publication date: August 24, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Pei-Yu CHOU, Yi-Ting FU, Ting-Gang CHEN, Tze-Liang LEE
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Patent number: 11652106Abstract: A semiconductor device includes a plurality of semiconductor fins, at least one gate stack, a refill isolation, and an air gap. Each of the semiconductor fins extends in an X direction. Two adjacent ones of the semiconductor fins are spaced apart from each other in a Y direction transverse to the X direction. The at least one gate stack has two stack sections spaced apart from each other in the Y direction. The stack sections are disposed over two adjacent ones of the semiconductor fins, respectively. The refill isolation and the air gap are disposed between the stack sections.Type: GrantFiled: May 6, 2021Date of Patent: May 16, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Pei-Yu Chou, Yi-Ting Fu, Ting-Gang Chen, Tze-Liang Lee
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Publication number: 20230015372Abstract: A method includes forming a fin protruding from a substrate, forming a first dielectric feature adjacent to the fin over the substrate, forming a cladding layer over the fin and the first dielectric feature, and removing a portion of the cladding layer to form an opening. The opening exposes the first dielectric feature. The method further includes forming a second dielectric feature adjacent to the cladding layer, the second dielectric feature filling the opening, forming a dummy gate stack over the fin and the second dielectric feature, forming source/drain (S/D) features in the fin adjacent to the dummy gate stack, and replacing the dummy gate stack and the cladding layer with a metal gate stack. The second dielectric feature divides the metal gate stack.Type: ApplicationFiled: May 4, 2022Publication date: January 19, 2023Inventors: Ming-Yuan Wu, Da-Wen Lin, Yi-Ting Fu, Hsu-Chieh Cheng, Min Jiao
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Publication number: 20220384262Abstract: The present disclosure describes fabricating devices with tunable gate height and effective capacitance. A method includes forming a first metal gate stack in a dummy region of a semiconductor substrate, the first metal gate stack including a first work function metal (WFM) layer; forming a second metal gate stack in an active device region of the semiconductor substrate, the second metal gate stack including a second WFM layer different than the first WFM layer; and performing a CMP process using a slurry including charged abrasive nanoparticles. The charged abrasive nanoparticles include a first concentration in the active device region different from a second concentration in the dummy region causing different polish rates in the active device region and dummy region. After the performing of the CMP process, the first metal gate stack has a first height different from a second height of the second metal gate stack.Type: ApplicationFiled: August 9, 2022Publication date: December 1, 2022Inventors: Ming-Chang Wen, Chang-Yun Chang, Keng-Yao Chen, Chen-Yu Tai, Yi-Ting Fu
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Patent number: 11508623Abstract: The present disclosure describes fabricating devices with tunable gate height and effective capacitance. A method includes forming a first metal gate stack in a dummy region of a semiconductor substrate, the first metal gate stack including a first work function metal (WFM) layer; forming a second metal gate stack in an active device region of the semiconductor substrate, the second metal gate stack including a second WFM layer different than the first WFM layer; and performing a CMP process using a slurry including a charged abrasive nanoparticles. The charged abrasive nanoparticles include a first concentration in the active device region different from a second concentration in the dummy region causing different polish rates in the active device region and dummy region. After the performing of the CMP process, the first metal gate stack has a first height greater different from a second height of the second metal gate stack.Type: GrantFiled: December 17, 2020Date of Patent: November 22, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ming-Chang Wen, Chang-Yun Chang, Keng-Yao Chen, Chen-Yu Tai, Yi-Ting Fu
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Publication number: 20220359515Abstract: A semiconductor device includes a plurality of semiconductor fins, at least one gate stack, a refill isolation, and an air gap. Each of the semiconductor fins extends in an X direction. Two adjacent ones of the semiconductor fins are spaced apart from each other in a Y direction transverse to the X direction. The at least one gate stack has two stack sections spaced apart from each other in the Y direction. The stack sections are disposed over two adjacent ones of the semiconductor fins, respectively. The refill isolation and the air gap are disposed between the stack sections.Type: ApplicationFiled: May 6, 2021Publication date: November 10, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Pei-Yu CHOU, Yi-Ting FU, Ting-Gang CHEN, Tze-Liang LEE
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Publication number: 20220285529Abstract: A method includes forming a first and a second dummy gate stack crossing over a semiconductor region, forming an ILD to embed the first and the second dummy gate stacks therein, replacing the first and the second dummy gate stacks with a first and a second replacement gate stack, respectively, performing a first etching process to form a first opening. A portion of the first replacement gate stack and a portion of the second replacement gate stack are removed. The method further includes filling the first opening to form a dielectric isolation region, performing a second etching process to form a second opening, with the ILD being etched, and the dielectric isolation region being exposed to the second opening, forming a contact spacer in the second opening, and filling a contact plug in the second opening. The contact plug is between opposite portions of the contact spacer.Type: ApplicationFiled: May 23, 2022Publication date: September 8, 2022Inventors: Ting-Gang Chen, Tai-Chun Huang, Ming-Chang Wen, Shu-Yuan Ku, Fu-Kai Yang, Tze-Liang Lee, Yung-Cheng Lu, Yi-Ting Fu
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Patent number: 11342444Abstract: A method includes forming a first and a second dummy gate stack crossing over a semiconductor region, forming an ILD to embed the first and the second dummy gate stacks therein, replacing the first and the second dummy gate stacks with a first and a second replacement gate stack, respectively, performing a first etching process to form a first opening. A portion of the first replacement gate stack and a portion of the second replacement gate stack are removed. The method further includes filling the first opening to form a dielectric isolation region, performing a second etching process to form a second opening, with the ILD being etched, and the dielectric isolation region being exposed to the second opening, forming a contact spacer in the second opening, and filling a contact plug in the second opening. The contact plug is between opposite portions of the contact spacer.Type: GrantFiled: September 19, 2019Date of Patent: May 24, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ting-Gang Chen, Tai-Chun Huang, Ming-Chang Wen, Shu-Yuan Ku, Fu-Kai Yang, Tze-Liang Lee, Yung-Cheng Lu, Yi-Ting Fu
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Patent number: 11107902Abstract: A method includes forming a first and a second dummy gate stack crossing over a semiconductor region, forming an ILD to embed the first and the second dummy gate stacks therein, replacing the first and the second dummy gate stacks with a first and a second replacement gate stack, respectively, performing a first etching process to form a first opening. A portion of the first replacement gate stack and a portion of the second replacement gate stack are removed. The method further includes filling the first opening to form a dielectric isolation region, performing a second etching process to form a second opening, with the ILD being etched, and the dielectric isolation region being exposed to the second opening, forming a contact spacer in the second opening, and filling a contact plug in the second opening. The contact plug is between opposite portions of the contact spacer.Type: GrantFiled: June 25, 2018Date of Patent: August 31, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ting-Gang Chen, Tai-Chun Huang, Yi-Ting Fu, Ming-Chang Wen, Shu-Yuan Ku, Fu-Kai Yang, Tze-Liang Lee, Yung-Cheng Lu
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Publication number: 20210202320Abstract: The present disclosure describes fabricating devices with tunable gate height and effective capacitance. A method includes forming a first metal gate stack in a dummy region of a semiconductor substrate, the first metal gate stack including a first work function metal (WFM) layer; forming a second metal gate stack in an active device region of the semiconductor substrate, the second metal gate stack including a second WFM layer different than the first WFM layer; and performing a CMP process using a slurry including a charged abrasive nanoparticles. The charged abrasive nanoparticles include a first concentration in the active device region different from a second concentration in the dummy region causing different polish rates in the active device region and dummy region. After the performing of the CMP process, the first metal gate stack has a first height greater different from a second height of the second metal gate stack.Type: ApplicationFiled: December 17, 2020Publication date: July 1, 2021Inventors: Ming-Chang Wen, Chang-Yun Chang, Keng-Yao Chen, Chen-Yu Tai, Yi-Ting Fu
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Publication number: 20200013875Abstract: A method includes forming a first and a second dummy gate stack crossing over a semiconductor region, forming an ILD to embed the first and the second dummy gate stacks therein, replacing the first and the second dummy gate stacks with a first and a second replacement gate stack, respectively, performing a first etching process to form a first opening. A portion of the first replacement gate stack and a portion of the second replacement gate stack are removed. The method further includes filling the first opening to form a dielectric isolation region, performing a second etching process to form a second opening, with the ILD being etched, and the dielectric isolation region being exposed to the second opening, forming a contact spacer in the second opening, and filling a contact plug in the second opening. The contact plug is between opposite portions of the contact spacer.Type: ApplicationFiled: September 19, 2019Publication date: January 9, 2020Inventors: Ting-Gang Chen, Tai-Chun Huang, Ming-Chang Wen, Shu-Yuan Ku, Fu-Kai Yang, Tze-Liang Lee, Yung-Cheng Lu, Yi-Ting Fu
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Publication number: 20190393324Abstract: A method includes forming a first and a second dummy gate stack crossing over a semiconductor region, forming an ILD to embed the first and the second dummy gate stacks therein, replacing the first and the second dummy gate stacks with a first and a second replacement gate stack, respectively, performing a first etching process to form a first opening. A portion of the first replacement gate stack and a portion of the second replacement gate stack are removed. The method further includes filling the first opening to form a dielectric isolation region, performing a second etching process to form a second opening, with the ILD being etched, and the dielectric isolation region being exposed to the second opening, forming a contact spacer in the second opening, and filling a contact plug in the second opening. The contact plug is between opposite portions of the contact spacer.Type: ApplicationFiled: June 25, 2018Publication date: December 26, 2019Inventors: Ting-Gang Chen, Tai-Chun Huang, Yi-Ting Fu, Ming-Chang Wen, Shu-Yuan Ku, Fu-Kai Yang, Tze-Liang Lee, Yung-Cheng Lu