Patents by Inventor Yi-Ting Shih

Yi-Ting Shih has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12113046
    Abstract: A method for preparing a semiconductor device includes providing an integrated circuit die having a bond pad. The bond pad includes aluminum (Al). The method also includes etching a top portion of the bond pad to form a recess, and bonding a wire bond to the recess in the bond pad. The wire bond includes copper (Cu).
    Type: Grant
    Filed: November 2, 2023
    Date of Patent: October 8, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Wei-Zhong Li, Yi-Ting Shih, Chien-Chung Wang, Hsih-Yang Chiu
  • Publication number: 20240063175
    Abstract: A method for preparing a semiconductor device includes providing an integrated circuit die having a bond pad. The bond pad includes aluminum (Al). The method also includes etching a top portion of the bond pad to form a recess, and bonding a wire bond to the recess in the bond pad. The wire bond includes copper (Cu).
    Type: Application
    Filed: November 2, 2023
    Publication date: February 22, 2024
    Inventors: WEI-ZHONG LI, YI-TING SHIH, CHIEN-CHUNG WANG, HSIH-YANG CHIU
  • Patent number: 11876072
    Abstract: A method for preparing a semiconductor device includes providing an integrated circuit die having a bond pad. The bond pad includes aluminum (Al). The method also includes etching a top portion of the bond pad to form a recess, and bonding a wire bond to the recess in the bond pad. The wire bond includes copper (Cu).
    Type: Grant
    Filed: September 2, 2021
    Date of Patent: January 16, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Wei-Zhong Li, Yi-Ting Shih, Chien-Chung Wang, Hsih-Yang Chiu
  • Publication number: 20230061312
    Abstract: A method for preparing a semiconductor device includes providing an integrated circuit die having a bond pad. The bond pad includes aluminum (Al). The method also includes etching a top portion of the bond pad to form a recess, and bonding a wire bond to the recess in the bond pad. The wire bond includes copper (Cu).
    Type: Application
    Filed: September 2, 2021
    Publication date: March 2, 2023
    Inventors: WEI-ZHONG LI, YI-TING SHIH, CHIEN-CHUNG WANG, HSIH-YANG CHIU
  • Patent number: 11538920
    Abstract: A method for increasing an oxide thickness at trench corner of an UMOSFET is provided, comprising providing an N-type substrate, and forming an N-type drift region, N-type and P-type heavily doped regions and P-type body therein. A trench is defined through lithography, and a pad oxide is formed along the trench through oxidation or deposition process. An oxidation barrier is formed upon the pad oxide. A thermal oxidation process is employed, so a corner oxide is effectively formed at the trench corner. After removing the pad oxide and oxidation barrier, various back-end processes are carried out to complete the transistor structure. The invention is aimed to increase oxide thickness near the trench bottom, and can be applied to high voltage devices, such as SiC. The conventional electric field crowding effect occurring at the trench corner is greatly solved, thus increasing breakdown voltages thereof.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: December 27, 2022
    Assignee: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Bing-Yue Tsui, Fang-Hsin Lu, Yi-Ting Shih
  • Publication number: 20220148923
    Abstract: A method for increasing an oxide thickness at trench corner of an UMOSFET is provided, comprising providing an N-type substrate, and forming an N-type drift region, N-type and P-type heavily doped regions and P-type body therein. A trench is defined through lithography, and a pad oxide is formed along the trench through oxidation or deposition process. An oxidation barrier is formed upon the pad oxide. A thermal oxidation process is employed, so a corner oxide is effectively formed at the trench corner. After removing the pad oxide and oxidation barrier, various back-end processes are carried out to complete the transistor structure. The invention is aimed to increase oxide thickness near the trench bottom, and can be applied to high voltage devices, such as SiC.
    Type: Application
    Filed: January 29, 2021
    Publication date: May 12, 2022
    Applicant: National Chiao Tung University
    Inventors: Bing-Yue Tsui, Fang-Hsin Lu, Yi-Ting Shih
  • Patent number: 9153389
    Abstract: Provided is a carbon nanotube-graphene composite comprising a substrate, a graphene layer disposed on the substrate, and a patterned layer of aligned carbon nanotubes disposed on the graphene layer.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: October 6, 2015
    Assignee: National Taiwan University of Science and Technology
    Inventors: Yi-Ting Shih, Ying-Sheng Huang, Kuei-Yi Lee
  • Publication number: 20150004373
    Abstract: Provided is a carbon nanotube-graphene composite comprising a substrate, a graphene layer disposed on the substrate, and a patterned layer of aligned carbon nanotubes disposed on the graphene layer.
    Type: Application
    Filed: June 27, 2013
    Publication date: January 1, 2015
    Inventors: Yi-Ting Shih, Ying-Sheng Huang, Kuei-Yi Lee