Patents by Inventor YI-TSANG HSIEH
YI-TSANG HSIEH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250069860Abstract: A method for manufacturing a semiconductor structure includes disposing a wafer in a processing chamber, in which the wafer is laterally surrounded by a focus ring. A plasma is formed in the processing chamber to process the wafer. A thickness of the focus ring is detected. A plasma direction of the plasma over a peripheral region of the wafer is adjusted according to the thickness of the focus ring.Type: ApplicationFiled: November 5, 2024Publication date: February 27, 2025Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Lun KE, Yu-Chi LIN, Yi-Tsang HSIEH, Yu-Hsi TANG, Chih-Teng LIAO
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Patent number: 12165851Abstract: A method for manufacturing a semiconductor structure includes disposing a wafer in a processing chamber, in which the wafer is laterally surrounded by a focus ring. A plasma is formed in the processing chamber to process the wafer. A thickness of the focus ring is detected. A plasma direction of the plasma over a peripheral region of the wafer is adjusted according to the thickness of the focus ring.Type: GrantFiled: July 29, 2021Date of Patent: December 10, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Lun Ke, Yu-Chi Lin, Yi-Tsang Hsieh, Yu-Hsi Tang, Chih-Teng Liao
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Publication number: 20240395508Abstract: A semiconductor manufacturing apparatus for performing a process is disclosed. An apparatus includes a chamber configured to receive a wafer for an etching process; a conductive focus ring disposed within the chamber and configured to focus an electric field to control an etch direction of the etching process; and an insulative cover ring disposed within the chamber, wherein the insulative cover ring is configured to modify the electric field, wherein the insulative cover ring has an inner annular insulative portion and outer annular insulative portion, and wherein a gap is defined between the inner annular insulative portion and the outer annular insulative portion.Type: ApplicationFiled: May 25, 2023Publication date: November 28, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hao Chen, Chung Chuan Huang, Yi-Tsang Hsieh, Yu-Chi Lin, Cha-Hsin Chao, Che-En Tsai
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Publication number: 20240387152Abstract: A plasma etching system generates a plasma above a wafer in a plasma etching chamber. The wafer is surrounded by a focus ring. The plasma etching system straightens a plasma sheath above the focus ring by generating a supplemental electric field above the focus ring.Type: ApplicationFiled: July 26, 2024Publication date: November 21, 2024Inventors: Po-Lung HUNG, Yi-Tsang HSIEH, Yu-Hsi TANG, Chih-Ching CHENG, Chih-Teng LIAO
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Publication number: 20240379387Abstract: In a method of controlling a plasma beam of a plasma etcher a flow rate controller of the plasma etcher is set to generate one or more flow rates of an etching gas corresponding to one or more plasma beams of the plasma etcher. The emitted light generated by plasma discharge corresponding to the one or more plasma beams of the plasma etcher is monitored. The flow rate controller is calibrated based on the one or more flow rates and a corresponding emitted light of the plasma discharge.Type: ApplicationFiled: July 24, 2024Publication date: November 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Lung HUNG, Yi-Tsang HSIEH, Yu-Hsi TANG, Chih-Teng LIAO, Chih-Ching CHENG
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Patent number: 12142494Abstract: In a method of controlling a plasma beam of a plasma etcher a flow rate controller of the plasma etcher is set to generate one or more flow rates of an etching gas corresponding to one or more plasma beams of the plasma etcher. The emitted light generated by plasma discharge corresponding to the one or more plasma beams of the plasma etcher is monitored. The flow rate controller is calibrated based on the one or more flow rates and a corresponding emitted light of the plasma discharge.Type: GrantFiled: June 7, 2021Date of Patent: November 12, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Po-Lung Hung, Yi-Tsang Hsieh, Yu-Hsi Tang, Chih-Teng Liao, Chih-Ching Cheng
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Publication number: 20230067400Abstract: A plasma etching system generates a plasma above a wafer in a plasma etching chamber. The wafer is surrounded by a focus ring. The plasma etching system straightens a plasma sheath above the focus ring by generating a supplemental electric field above the focus ring.Type: ApplicationFiled: August 30, 2021Publication date: March 2, 2023Inventors: Po-Lung HUNG, Yi-Tsang HSIEH, Yu-Hsi TANG, Chih-Ching CHENG, Chih-Teng LIAO
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Publication number: 20230036955Abstract: A method for manufacturing a semiconductor structure includes disposing a wafer in a processing chamber, in which the wafer is laterally surrounded by a focus ring. A plasma is formed in the processing chamber to process the wafer. A thickness of the focus ring is detected. A plasma direction of the plasma over a peripheral region of the wafer is adjusted according to the thickness of the focus ring.Type: ApplicationFiled: July 29, 2021Publication date: February 2, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Lun KE, Yu-Chi LIN, Yi-Tsang HSIEH, Yu-Hsi TANG, Chih-Teng LIAO
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Patent number: 11532515Abstract: A method includes forming a bottom source/drain contact plug in a bottom inter-layer dielectric. The bottom source/drain contact plug is electrically coupled to a source/drain region of a transistor. The method further includes forming an inter-layer dielectric overlying the bottom source/drain contact plug. A source/drain contact opening is formed in the inter-layer dielectric, with the bottom source/drain contact plug exposed through the source/drain contact opening. A dielectric spacer layer is formed to have a first portion extending into the source/drain contact opening and a second portion over the inter-layer dielectric. An anisotropic etching is performed on the dielectric spacer layer, and a remaining vertical portion of the dielectric spacer layer forms a source/drain contact spacer. The remaining portion of the source/drain contact opening is filled to form an upper source/drain contact plug.Type: GrantFiled: October 9, 2020Date of Patent: December 20, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Tsang Hsieh, Cha-Hsin Chao, Yi-Wei Chiu, Li-Te Hsu, Ying Ting Hsia
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Publication number: 20220392785Abstract: In a method of controlling a plasma beam of a plasma etcher a flow rate controller of the plasma etcher is set to generate one or more flow rates of an etching gas corresponding to one or more plasma beams of the plasma etcher. The emitted light generated by plasma discharge corresponding to the one or more plasma beams of the plasma etcher is monitored. The flow rate controller is calibrated based on the one or more flow rates and a corresponding emitted light of the plasma discharge.Type: ApplicationFiled: June 7, 2021Publication date: December 8, 2022Inventors: Po-Lung HUNG, Yi-Tsang HSIEH, Yu-Hsi TANG, Chih-Teng LIAO, Chih-Ching CHENG
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Publication number: 20210028062Abstract: A method includes forming a bottom source/drain contact plug in a bottom inter-layer dielectric. The bottom source/drain contact plug is electrically coupled to a source/drain region of a transistor. The method further includes forming an inter-layer dielectric overlying the bottom source/drain contact plug. A source/drain contact opening is formed in the inter-layer dielectric, with the bottom source/drain contact plug exposed through the source/drain contact opening. A dielectric spacer layer is formed to have a first portion extending into the source/drain contact opening and a second portion over the inter-layer dielectric. An anisotropic etching is performed on the dielectric spacer layer, and a remaining vertical portion of the dielectric spacer layer forms a source/drain contact spacer. The remaining portion of the source/drain contact opening is filled to form an upper source/drain contact plug.Type: ApplicationFiled: October 9, 2020Publication date: January 28, 2021Inventors: Yi-Tsang Hsieh, Cha-Hsin Chao, Yi-Wei Chiu, Li-Te Hsu, Ying Ting Hsia
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Patent number: 10804149Abstract: A method includes forming a bottom source/drain contact plug in a bottom inter-layer dielectric. The bottom source/drain contact plug is electrically coupled to a source/drain region of a transistor. The method further includes forming an inter-layer dielectric overlying the bottom source/drain contact plug. A source/drain contact opening is formed in the inter-layer dielectric, with the bottom source/drain contact plug exposed through the source/drain contact opening. A dielectric spacer layer is formed to have a first portion extending into the source/drain contact opening and a second portion over the inter-layer dielectric. An anisotropic etching is performed on the dielectric spacer layer, and a remaining vertical portion of the dielectric spacer layer forms a source/drain contact spacer. The remaining portion of the source/drain contact opening is filled to form an upper source/drain contact plug.Type: GrantFiled: July 25, 2018Date of Patent: October 13, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Tsang Hsieh, Cha-Hsin Chao, Yi-Wei Chiu, Li-Te Hsu, Ying Ting Hsia
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Publication number: 20200070573Abstract: A bicycle hub shaft includes a first shaft section made of a first material and inserted into a sprocket seat; and a second shaft section made of a second material. The strength of the first material is stronger than that of the second material. The first shaft section has one end connected to one end of the second shaft section. The bicycle hub shaft is formed by the first and second shaft sections, instead of being integrally formed. Besides, the strength of the first shaft section is stronger than the second shaft section, so that the first shaft section inserted in the sprocket seat has a higher structural strength, thus improving the strength of the bicycle hub shaft and the load capacity of the sprocket seat as well.Type: ApplicationFiled: September 3, 2018Publication date: March 5, 2020Inventor: Yi-Tsang HSIEH
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Patent number: 10510598Abstract: A method includes forming a bottom source/drain contact plug in a bottom inter-layer dielectric. The bottom source/drain contact plug is electrically coupled to a source/drain region of a transistor. The method further includes forming an inter-layer dielectric overlying the bottom source/drain contact plug. A source/drain contact opening is formed in the inter-layer dielectric, with the bottom source/drain contact plug exposed through the source/drain contact opening. A dielectric spacer layer is formed to have a first portion extending into the source/drain contact opening and a second portion over the inter-layer dielectric. An anisotropic etching is performed on the dielectric spacer layer, and a remaining vertical portion of the dielectric spacer layer forms a source/drain contact spacer. The remaining portion of the source/drain contact opening is filled to form an upper source/drain contact plug.Type: GrantFiled: December 21, 2016Date of Patent: December 17, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Tsang Hsieh, Cha-Hsin Chao, Yi-Wei Chiu, Li-Te Hsu, Ying Ting Hsia
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Publication number: 20190006236Abstract: A method includes forming a bottom source/drain contact plug in a bottom inter-layer dielectric. The bottom source/drain contact plug is electrically coupled to a source/drain region of a transistor. The method further includes forming an inter-layer dielectric overlying the bottom source/drain contact plug. A source/drain contact opening is formed in the inter-layer dielectric, with the bottom source/drain contact plug exposed through the source/drain contact opening. A dielectric spacer layer is formed to have a first portion extending into the source/drain contact opening and a second portion over the inter-layer dielectric. An anisotropic etching is performed on the dielectric spacer layer, and a remaining vertical portion of the dielectric spacer layer forms a source/drain contact spacer. The remaining portion of the source/drain contact opening is filled to form an upper source/drain contact plug.Type: ApplicationFiled: July 25, 2018Publication date: January 3, 2019Inventors: Yi-Tsang Hsieh, Cha-Hsin Chao, Yi-Wei Chiu, Li-Te Hsu, Ying Ting Hsia
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Publication number: 20180174904Abstract: A method includes forming a bottom source/drain contact plug in a bottom inter-layer dielectric. The bottom source/drain contact plug is electrically coupled to a source/drain region of a transistor. The method further includes forming an inter-layer dielectric overlying the bottom source/drain contact plug. A source/drain contact opening is formed in the inter-layer dielectric, with the bottom source/drain contact plug exposed through the source/drain contact opening. A dielectric spacer layer is formed to have a first portion extending into the source/drain contact opening and a second portion over the inter-layer dielectric. An anisotropic etching is performed on the dielectric spacer layer, and a remaining vertical portion of the dielectric spacer layer forms a source/drain contact spacer. The remaining portion of the source/drain contact opening is filled to form an upper source/drain contact plug.Type: ApplicationFiled: December 21, 2016Publication date: June 21, 2018Inventors: Yi-Tsang Hsieh, Cha-Hsin Chao, Yi-Wei Chiu, Li-Te Hsu, Ying Ting Hsia
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Patent number: 8607100Abstract: A motherboard testing device applied to a motherboard which includes two memory channels, and a CPU. Each of the two memory channels includes two memory slots. The motherboard testing device includes four memory modules received in the four memory slots, a switching chip, a microcontroller, and a testing module. The switching chip includes four input pins electrically connected to the four memory modules, four output pins electrically connected to the CPU, and a controlling pin electrically connected to the microcontroller. The microcontroller forms a plurality of combination modes of the memory slots by electrically combining the four memory slots, and controls the switching chip to electrically connect memory slots of each combination mode to the CPU. The testing module tests whether the CPU controls the memory modules received in the memory slots of each combination mode to work in proper working modes.Type: GrantFiled: December 30, 2011Date of Patent: December 10, 2013Assignee: Hon Hai Precision Industry Co., Ltd.Inventors: Yi-Tsang Hsieh, Yung-Po Chang
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Publication number: 20130073906Abstract: A motherboard testing device applied to a motherboard which includes two memory channels, and a CPU. Each of the two memory channels includes two memory slots. The motherboard testing device includes four memory modules received in the four memory slots, a switching chip, a microcontroller, and a testing module. The switching chip includes four input pins electrically connected to the four memory modules, four output pins electrically connected to the CPU, and a controlling pin electrically connected to the microcontroller. The microcontroller forms a plurality of combination modes of the memory slots by electrically combining the four memory slots, and controls the switching chip to electrically connect memory slots of each combination mode to the CPU. The testing module tests whether the CPU controls the memory modules received in the memory slots of each combination mode to work in proper working modes.Type: ApplicationFiled: December 30, 2011Publication date: March 21, 2013Applicant: HON HAI PRECISION INDUSTRY CO., LTD.Inventors: YI-TSANG HSIEH, YUNG-PO CHANG