Abstract: An electronic element packaging module including a lead frame, an insulating layer and at least one electronic element is provided. The lead frame is a patterned metal sheet and has a first surface, a second surface opposite thereto and a through trench passing from the first surface to the second surface. A substrate portion and a plurality of lead portions around the substrate portion of the lead frame are defined by the through trench. The second surface of the lead frame is exposed outside the electronic element packaging module. The insulating layer disposed in the through trench has a third surface and a forth surface substantially coplanar with the first and the second surfaces, respectively. The electronic element disposed on the first surface is coupled to the lead frame.

Abstract: A method of depositing a copper interconnection layer on a substrate for use in a flat panel display interconnection system, comprising the steps of: a) coating said substrate with a photoresist layer; b) patterning said photoresist layer to obtain a patterned photoresist substrate comprising at least one trench patterned into said photoresist layer; c) providing a first catalyzation layer onto the patterned photoresist substrate; d) providing an electroless plated layer of an insulation layer deposited onto said first catalyzation layer; e) removing the successively superimposed photoresist layer, catalyzation layer and insulation layer except in the at least one trench, to obtain a pattern of the first catalyzation layer with an insulation layer deposited thereon.

Abstract: An electronic element packaging module including a lead frame, an insulating layer and at least one electronic element is provided. The lead frame is a patterned metal sheet and has a first surface, a second surface opposite thereto and a through trench passing from the first surface to the second surface. A substrate portion and a plurality of lead portions around the substrate portion of the lead frame are defined by the through trench. The second surface of the lead frame is exposed outside the electronic element packaging module. The insulating layer disposed in the through trench has a third surface and a forth surface substantially coplanar with the first and the second surfaces, respectively. The electronic element disposed on the first surface is coupled to the lead frame.

Abstract: Electroless NiWP layers are used for TFT Cu gate process. The NiWP deposition process comprises the following steps. (a) Cleaning of the base surface using for example UV light, ozone solution and/or alkaline mixture solution, (b) micro-etching of the base surface using, e.g. diluted acid, (c) catalyzation of the base surface using, e.g. SnCl<SUB>2</SUB> and PdCl<SUB>2</SUB> solutions, (d) conditioning of the base surface using reducing agent solution, and (e) NiWP deposition. It has been discovered that NiWP layers deposited under certain conditions could provide good adhesion to the glass substrate and to the Cu layer with a good Cu barrier capability. A NiWP layer in useful for adhesion, capping and/or barrier layers for TFT Cu gate process (e.g. for flat screen display panels).

Abstract: Methods and apparatus for producing a copper layer on substrate in a flat panel display manufacturing process, where the copper is electrodelessly deposited on a substrate to form a copper interconnection layer. A copper solution containing: CuSO4 5H2O as a copper source, potassium sodium tartrate or trisodium citrate as a complexing agent, glyoxylate, glyoxilic acid or sodium phosphate as a reducing agent, a sulfur organic compound as a stabilizing agent, and a pH adjusting agent, is used to form the copper interconnection layer on the substrate.