Patents by Inventor Yi-Tsung Jan
Yi-Tsung Jan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9263281Abstract: A method for manufacturing a contact plug is provided. The method includes providing a silicon substrate having at least one opening. A titanium layer is conformably formed in the opening. A first barrier layer is conformably formed on the titanium layer in the opening. A rapid thermal process is performed on the titanium layer and the first barrier layer. After performing the rapid thermal process, a second barrier layer is conformably formed on the first barrier layer in the opening.Type: GrantFiled: August 30, 2013Date of Patent: February 16, 2016Assignee: Vanguard International Semiconductor CorporationInventors: Yi-Tsung Jan, Peng-Fei Wu, Chih-Ming Kao, You-Cheng Liau, Wen-Jen Chuang, Rong-Gen Wu, Huan-Yu Chien, Ting-Yu Kuo, Su-Chen Lin
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Publication number: 20150061082Abstract: A method for manufacturing a contact plug is provided. The method includes providing a silicon substrate having at least one opening. A titanium layer is conformably formed in the opening. A first barrier layer is conformably formed on the titanium layer in the opening. A rapid thermal process is performed on the titanium layer and the first barrier layer. After performing the rapid thermal process, a second barrier layer is conformably formed on the first barrier layer in the opening.Type: ApplicationFiled: August 30, 2013Publication date: March 5, 2015Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Yi-Tsung JAN, Peng-Fei WU, Chih-Ming KAO, You-Cheng LIAU, Wen-Jen CHUANG, Rong-Gen WU, Huan-Yu CHIEN, Ting-Yu KUO, Su-Chen LIN
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Publication number: 20090134455Abstract: A semiconductor device including a substrate, a first well, a second well, a gate, a first doped region, and a second doped region. The substrate includes a first conductive type. The first well includes a second conductive type and is formed in the substrate. The second well includes the second conductive type and is formed in the substrate. The gate is formed on the substrate and overlaps the first and the second wells. The first doped region includes the second conductive type. The first doped region is formed in the first well and self-aligned with the gate. The second doped region includes the second conductive type. The second doped region is formed in the second well and self-aligned with the gate. The gate, the first and the second doped regions constitute a transistor.Type: ApplicationFiled: November 27, 2007Publication date: May 28, 2009Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Shih-Fang Lin, Meng-Yen Hsieh, Yi-Tsung Jan, Sung-Min Wei, Chia-Yi Lee, Chun-Yao Li, Han-Lung Tsai, Zhe-Xiong Wu, Wen-Tsung Wang
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Publication number: 20090053891Abstract: A method for fabricating a semiconductor device for preventing a poisoned via is provided. A substrate with a conductive layer formed thereon is provided. A composite layer is formed over the substrate and the conductive layer, wherein the composite layer comprises a dielectric layer and a spin-on-glass layer. A via hole is formed through the composite layer, wherein the via hole exposes a surface of the conductive layer. A protection layer is formed on a sidewall of the via hole so as to prevent out-gassing from the spin-on-glass layer. A barrier layer is formed on the protection layer and the conductive layer within the via hole. And a metal layer is deposited on the barrier layer within the via hole to fill the via hole.Type: ApplicationFiled: August 22, 2008Publication date: February 26, 2009Applicant: VANGUARD INTERNATIONAL SEMICONDUCTORInventors: Yi-Chin Lin, Chia-Wei Hsu, Yeou-Bin Lin, Yi-Tsung Jan, Sung-Min Wei, Chin-Cherng Liao, Pi-Xuang Chuang, Shih-Ming Chen, Hsiao-Ying Yang
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Patent number: 6835636Abstract: A method for fabricating source/drain devices. A semiconductor substrate is provided with a gate formed on the semiconductor substrate, and a hard mask layer formed on the gate. A first doped area is formed on a first side of the gate on the semiconductor substrate, and a second doped area is formed on a second side of the gate on the semiconductor substrate in a manner such that the second doped area is separated from the gate by a predetermined distance. A patterned photo resist layer is formed on the semiconductor substrate having an opening on the second side, the exposed gate equal to half the width of the gate. The semiconductor substrate is implanted and annealed to form a dual diffusion area on the second side of the gate using the patterned photo resist layer and the hard mask layer as masks.Type: GrantFiled: December 11, 2002Date of Patent: December 28, 2004Assignee: Vanguard International Semiconductor CorporationInventors: Yi-Tsung Jan, Wen-Tsung Wang, Sung-Min Wei, Chih-Cherng Liao, Zhe-Xiong Wu, Mao-Tsang Chen, Yuan-Heng Li
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Patent number: 6713338Abstract: A method for fabricating source/drain devices. A semiconductor substrate is provided with a gate formed thereon, a first doped area is formed on a first side of the gate on the semiconductor substrate, and a second doped area is formed on a second side of the gate on the semiconductor substrate in a manner such that the second doped area is separated from the gate by a predetermined distance. A patterned photo resist layer is formed on the semiconductor substrate having an opening on the second side, the exposed gate less than half the width of the gate. The semiconductor substrate is implanted and annealed to form a dual diffusion area on the second side of the gate using the patterned photo resist layer as a mask.Type: GrantFiled: December 11, 2002Date of Patent: March 30, 2004Assignee: Vanguard International Semiconductor CorporationInventors: Wen-Tsung Wang, Yi-Tsung Jan, Sung-Min Wei, Chih-Cherng Liao, Zhe-Xiong Wu, Mao-Tsung Chen, Yuan-Heng Li
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Publication number: 20040043589Abstract: A method for fabricating source/drain devices. A semiconductor substrate is provided with a gate formed on the semiconductor substrate, and a hard mask layer formed on the gate. A first doped area is formed on a first side of the gate on the semiconductor substrate, and a second doped area is formed on a second side of the gate on the semiconductor substrate in a manner such that the second doped area is separated from the gate by a predetermined distance. A patterned photo resist layer is formed on the semiconductor substrate having an opening on the second side, the exposed gate equal to half the width of the gate. The semiconductor substrate is implanted and annealed to form a dual diffusion area on the second side of the gate using the patterned photo resist layer and the hard mask layer as masks.Type: ApplicationFiled: December 11, 2002Publication date: March 4, 2004Inventors: Yi-Tsung Jan, Wen-Tsung Wang, Sung-Min Wei, Chih-Cherng Liao, Zhe-Xiong Wu, Mao-Tsang Chen, Yuan-Heng Li
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Publication number: 20040038484Abstract: A method for fabricating source/drain devices. A semiconductor substrate is provided with a gate formed thereon, a first doped area is formed on a first side of the gate on the semiconductor substrate, and a second doped area is formed on a second side of the gate on the semiconductor substrate in a manner such that the second doped area is separated from the gate by a predetermined distance. A patterned photo resist layer is formed on the semiconductor substrate having an opening on the second side, the exposed gate less than half the width of the gate. The semiconductor substrate is implanted and annealed to form a dual diffusion area on the second side of the gate using the patterned photo resist layer as a mask.Type: ApplicationFiled: December 11, 2002Publication date: February 26, 2004Inventors: Wen-Tsung Wang, Yi-Tsung Jan, Sung-Min Wei, Chih-Cherng Liao, Zhe-Xiong Wu, Mao-Tsung Chen, Yuan-Heng Li