Abstract: A method of fabricating a color filter is provided, which includes the following steps. First, a loose composite film is formed. Next, the loose composite film is patterned to form a patterned composite film. Then, a treatment process is performed to dense the patterned composite film, thereby a color filter is formed.

Abstract: An image sensor is provided. The image sensor includes a plurality of photodiode doped regions in a substrate, a passivation layer above the substrate, a dielectric layer between the passivation layer and the substrate, and a plurality of color filters in the dielectric layer being corresponding to the photodiode doped regions.

Abstract: A method for fabricating a color filter is disclosed. First, a substrate having a dielectric layer and a passivation thereon is provided. Next, a first pattern transfer process is performed to form a trench in the dielectric layer and the passivation layer, and a color filter is formed in the trench, in which the color filter partially covers the surface of the passivation layer. Next, a chemical mechanical polishing process is performed to planarize the color filter, such that the surface of the color filter is even with the surface of the passivation layer.

Abstract: A method of improving the flatness of a microdisplay surface. A reflective mirror layer and a raised layer are formed in order on a semiconductor substrate. The raised layer may comprise a buffer layer and a stop layer, and pixel electrode areas are defined therefrom and gaps are consequently formed among the pixel electrode areas. A dielectric layer is deposited on the pixel electrode areas and fills the gaps. A dielectric layer is partially removed such that the portion on the raised layer is completely removed and the portion filling the gaps are partially removed, thereby the remaining dielectric layer in the gaps has a height not lower than the top of the mirror layer. Thereafter, the raised layer is entirely or partially removed. A transparent conductive layer may be further combined onto the semiconductor substrate and a liquid crystal filling process is performed to form an LCoS display panel.

Abstract: A method of manufacturing a dichroic filter array is provided and comprises forming a first dichroic filter material layer on a substrate, and then forming a patterned photoresist layer on the first dichroic filter material layer. The exposed portion of the first dichroic filter material layer is removed so as to form a plurality of first dichroic filter units. A second dichroic filter material layer is formed on the substrate and the patterned photoresist layer. The patterned photoresist layer and the second dichroic filter material layer located on the patterned photoresist layer are removed, and the second dichroic filter material layer between the first dichroic filter units are transformed into a plurality of second dichroic filter units. By using etching process and the lift-off process to simultaneously remove redundant dichroic filter material and the photoreisit layer, the multi-chroic filter array device with a relatively small volume can be rapidly produced.

Abstract: The invention is directed to a method for etching a color filter. The method comprises steps of providing a substrate having a multilayered filter material layer formed thereon and then disposing the substrate into an etching chamber with introducing a gas mixture into the etching chamber for performing a dry etching process so as to pattern the multilayered filter material layer, wherein the gas mixture comprises a physical reactive gas and a chemical reactive gas.

Abstract: A method of manufacturing liquid crystal alignment film includes performing an ion implantation process after providing a layer of organic or inorganic material on a substrate for performing an alignment treatment on the layer of organic or inorganic material is provided. Since the alignment treatment is a kind of non-contact method, it can lower the probability of damaging the organic alignment film and prevent generating powders and particles. Furthermore, the layer of inorganic material is formed on the substrate prior to the alignment treatment, so the inorganic material layer can be patterned before the alignment treatment.

Abstract: A process for fabricating a micro-display is provided. First, a wafer having a driving circuit thereon is provided. Then, a metallic reflective layer is formed on the wafer. Thereafter, an anti-reflection layer and a patterned photoresist layer are sequentially formed on the metallic reflective layer. Using the patterned photoresist layer as an etching mask, the anti-reflection layer and the metallic reflective layer are etched to form a trench pattern that exposes the surface of the wafer. After that, the patterned photoresist layer is removed. A dielectric layer is formed to cover the anti-reflection layer and fill the trench pattern. Then, a portion of the dielectric layer and the anti-reflection layer are removed to expose the surface of the metallic reflective layer.

Abstract: A method for manufacturing a back panel on a substrate is provided. The substrate has at least a switching device formed therein and a dielectric layer structure formed thereon. An interconnect structure is also formed in the dielectric layer structure. The method of forming the back panel comprises the step of performing an alloying process. After the alloying process, a pixel mirror layer is formed over the substrate. The pixel mirror layer is electrically connected to the switching device through the interconnect structure. A planar passivation layer is formed on the pixel mirror layer. Then, the planar passivation layer is patterned to expose a portion of the pixel mirror layer.

Abstract: A process of physical vapor depositing mirror layer with improved reflectivity is disclosed. A wafer is loaded into a PVD tool comprising a degas chamber, a Ti/TiN sputter deposition chamber, a cooling chamber, and an aluminum sputter deposition chamber. A wafer degas process is first performed within the degas chamber. The wafer is then transferred to the Ti/TiN sputter deposition chamber and deposition sputtering a layer of titanium onto the wafer. The wafer is transferred to the cooling chamber and gas cooling the wafer temperature down to 40-50° C. The wafer is then transferred to the aluminum sputter deposition chamber and deposition sputtering a layer of aluminum onto the wafer at 40-50° C. with a backside gas turned off. The deposited layer of aluminum over the wafer has a reflectivity of about 0.925 at wavelength of around 380 nm.

Abstract: A pixel array structure is provided. The pixel array structure comprises a plurality of pixel units and a plurality of dielectric walls. Each dielectric wall is disposed between two neighboring pixel units, wherein each pixel unit comprises at least one organic light emitting diode and a complementary metal-oxide-semiconductor (CMOS). The organic light emitting diode comprises a transparent electrode, a bottom electrode, and a light emitting material between the transparent electrode and the bottom electrode. The CMOS is disposed in a substrate. The substrate comprises a top-metal-layer structure located thereon and the top-metal-layer structure comprises an upmost top metal layer. Further, the bottom electrode of the CMOS is the upmost top metal layer of the top-metal-layer structure and the upmost top metal layer is a titanium metal layer.

Abstract: The present invention discloses a method for fabricating a buried bit line of a mask ROM. The method includes providing a semiconductor substrate with a photoresist layer, and patterning the photoresist layer to form a photoresist pattern. A first ion implantation process is performed to form a first doped region in the semiconductor substrate not covered by the photoresist pattern. Then, an organic layer is coated on the photoresist pattern and the semiconductor substrate and an etching process is performed to form an organic spacer at two sides of the photoresist pattern. Finally, a second ion implantation process forms a second doped region in the semiconductor substrate not covered by the photoresist pattern and the organic spacer. Finally, the photoresist pattern and the organic spacer are removed.

Abstract: The present invention discloses a method for fabricating a buried bit line of a mask ROM. The method includes providing a semiconductor substrate with a photoresist layer, and patterning the photoresist layer to form a photoresist pattern. A first ion implantation process is performed to form a first doped region in the semiconductor substrate not covered by the photoresist pattern. Then, an organic layer is coated on the photoresist pattern and the semiconductor substrate and an etching process is performed to form an organic spacer at two sides of the photoresist pattern. Finally, a second ion implantation process forms a second doped region in the semiconductor substrate not covered by the photoresist pattern and the organic spacer. Finally, the photoresist pattern and the organic spacer are removed.

Abstract: A method of fabricating a bottom electrode is provided. A dielectric layer comprising a first opening is formed on the substrate. A conductive layer is formed on the dielectric layer to fill the first opening. A first patterned mask layer comprising a second opening is formed on the conductive layer. An isotropic etching step is performed on the conductive layer with the first patterned mask layer serving as a mask. A recess with a non-vertical sidewall is formed on the conductive layer under the second opening. The first patterned mask layer is removed. The conductive layer is patterned to form a bottom electrode with the recess. A hemispherical grained silicon layer is formed on the bottom electrode.

Abstract: A method for fabricating a bottom electrode is provided. In this method a dielectric layer is formed on a substrate having a source/drain region. A via hole is formed in the dielectric layer to expose the source/drain region. A patterned, doped polysilicon layer is formed on the dielectric layer and fills the via hole, wherein the cross-section of the patterned doped polysilicon layer is arced or polygonal. The surface of the patterned polysilicon layer is transformed into an amorphous silicon layer. A hemispherical-grain layer is formed on the amorphous silicon layer.

Abstract: The present invention relates to a method of making a load resistor of a static random access memory on a dielectric layer of a semiconductor wafer. This method comprises depositing a poly-silicon layer on the dielectric layer, depositing a silicon-oxy-nitride (SiO.sub.X N.sub.Y) layer on the poly-silicon layer, performing a photolithographic process to define an area for making the load resistor, and performing an etching process to remove the silicon-oxy-nitride layer and the poly-silicon layer in all areas except for the area of the load resistor so as to form the load resistor. The poly-silicon layer of the load resistor is used as a conductive resistance layer, and the silicon-oxy-nitride layer of the load resistor is used as a radiation insulating layer for preventing radiation damages of the load resistor caused by plasma radiation in plasma processes to be performed later on.